Stacked Nanosheet Channel Structure With Extended Source/Drain Diffusion
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Solution Overview
Problem
The semiconductor industry faces challenges in improving processing and manufacturing efficiency as the complexity of semiconductor integrated circuits (ICs) increases with smaller geometries and higher functional density, leading to complex manufacturing processes.
Innovation Solution
A semiconductor device structure is manufactured using a stack of semiconductor layers with alternating first and second semiconductor layers, where the first layers form nanostructure channels and the second layers define vertical distances, with a gate electrode layer surrounding the channels, and thermal annealing is performed to diffuse dopants and form extended source/drain regions, optimizing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent divides the semiconductor structure into multiple alternating semiconductor layers (first semiconductor layers forming channels and second semiconductor layers acting as spacers), enabling complex functionality to be achieved through repeated modular units rather than monolithic complex structures, thus managing processing complexity while maintaining scaling benefits
Solution Approach 2:
The patent transitions from planar device architecture to vertically stacked three-dimensional architecture with alternating layers extending in the vertical direction, allowing increased functional density without proportionally increasing lateral processing complexity
2Quantity of substance
If functional density is increased with smaller geometries, then more circuits fit per chip area, but manufacturing process complexity increases
Solution Approach 1:
The patent implements nested structures where gate electrode layers surround and enclose channel-forming semiconductor layers in a gate-all-around configuration, with multiple such structures stacked vertically, allowing high functional density within a compact volume while using standardized repeating manufacturing units
Solution Approach 2:
The manufacturing process is segmented into discrete steps for forming alternating layers, with each layer pair representing a modular unit that can be replicated, making the complex high-density structure achievable through repeated application of simpler process modules
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by reducing channel resistance, improving current drive, and reducing contact resistance, while maintaining manufacturing efficiency and cost-effectiveness.
Implementation Method 1
thermal annealing is performed to diffuse dopants and form extended source/drain regions
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a source/drain epitaxial feature having a first semiconductor material, a first semiconductor layer having a first doped region and a first undoped region adjacent the first doped region, and the first doped region is in contact with the first semiconductor material. The structure further includes a second semiconductor layer disposed over the first semiconductor layer, and the second semiconductor layer includes a second doped region and a second undoped region adjacent the second doped region. The second doped region is in contact with the first semiconductor material. The structure further includes a gate electrode layer surrounding at least the first undoped region and the second undoped region.