Stacked Nanosheet Transistor Layout for Semiconductor Miniaturization
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Solution Overview
Problem
Existing semiconductor technologies have limitations in achieving further miniaturization of semiconductor devices.
Innovation Solution
A semiconductor device structure is designed with stacked transistors and nanosheets arranged in specific configurations, including insulating walls and gate electrodes, to facilitate further miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional planar transistor structures are used, then manufacturing and design are simpler, but further miniaturization cannot be achieved
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional stacked structures where multiple transistor layers are vertically arranged. This dimensional change enables continued miniaturization by utilizing the vertical space above the substrate rather than only expanding horizontally, thereby reducing the footprint area while maintaining functional transistor operations across multiple stacked layers
2Length of moving object
If stacked transistor structures are implemented, then miniaturization is enabled, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning and alignment procedures where mandrel structures are formed first, followed by precise deposition and etching steps that reference these pre-formed structures. This preliminary action establishes alignment markers and structural guides before the actual transistor formation, ensuring that subsequent layers align correctly even at reduced dimensions
Solution Approach 2:
The stacked transistor structure implements a nested arrangement where multiple transistor layers are vertically integrated with shared components. The insulating walls and gate structures are nested between semiconductor layers, allowing precise vertical stacking while reducing the need for extensive lateral alignment between independently fabricated components
3Reliability
If insulating walls are added between channels, then device functionality is improved, but device complexity increases
Solution Approach 1:
The patent divides the semiconductor channel into multiple discrete regions separated by insulating walls. This segmentation creates independent nanosheet channels between the walls, allowing each channel to function independently while sharing common gate control. The segmentation improves device functionality by enabling better electrical isolation and controlled carrier flow, while the walls are integrated into the existing stack architecture rather than added as separate complex components
Data Source
AI summary
A semiconductor device includes, above a substrate, a first layer with, on both sides in a direction, first regions; a second layer above the first layer with, on both sides in the direction, second regions above the first regions; a third layer, third regions, a fourth layer, and fourth regions, corresponding to the first layer, first regions, second layer, and second regions, respectively, the third layer being side by side with the first layer in another direction, the fourth layer being side by side with the second layer in the other direction; first and second gate electrodes above the first and second layers and the third and fourth layers, and having gate insulating films between these gate electrodes and these layers; and an insulating wall extending in the direction with both side surfaces contacted by the first and second layers and the third and fourth layers, respectively.