Vertically Stacked Nanowire FET Fabrication for High Density

The patent transitions from planar (2D) FET arrangement to vertically stacked (3D) configuration by forming multiple nanowire channels at different heights on the substrate. The gate structures wrap around nanowires at multiple vertical levels, enabling three-dimensional spatial utilization and significantly increasing device density without proportionally increasing manufacturing complexity.

The patent implements nested structures where gate dielectric layers and gate electrode structures are conformally deposited around nanowire channels at multiple vertical levels. The gate structures essentially nest around the nanowires in a cylindrical configuration, with insulator layers nested between conductive elements, creating a compact multi-layered vertical stack that maximizes space utilization.

The patent employs preliminary patterning actions where sacrificial layers are first deposited and patterned to define the vertical positions and shapes of nanowire channels before the actual semiconductor material is formed. Dummy gate structures are also preliminarily formed to establish alignment references for subsequent precise patterning steps, ensuring that critical dimensions are controlled with high precision throughout the fabrication process.

The patent uses sacrificial layers as intermediary structures that temporarily occupy space during fabrication and are later removed to create the final nanowire channel structures. These intermediary sacrificial layers enable precise definition of channel geometries and facilitate the formation of complex vertical stacks through sequential deposition and removal steps, thereby maintaining manufacturing precision while achieving high device density.