Stacked Neuromorphic Devices via TSVs for AI Performance
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Solution Overview
Problem
Current neuromorphic computing systems face limitations in performance due to the complexity of neural networks and the need for efficient data transmission and weight storage, which are not adequately addressed by existing semiconductor circuits.
Innovation Solution
A stacked neuromorphic device configuration with logic and core dies connected via through silicon vias (TSVs), where neuromorphic core dies include synapse arrays for weight storage and calculation, and a control circuit for data transmission, enhancing the performance of artificial intelligence calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If neuromorphic computing systems use complex neural networks with multiple layers, then AI performance and calculation capability are improved, but data transmission complexity and latency increase
Solution Approach 1:
The patent transitions from a planar 2D architecture to a 3D stacked architecture by vertically stacking multiple core dies. This dimensional change allows neural network layers to be distributed across different vertical levels, with each core die handling specific layers. The TSVs provide vertical interconnects that reduce transmission distance and complexity compared to horizontal routing in 2D, thereby improving AI performance while managing data transmission complexity.
Solution Approach 2:
The patent divides the neuromorphic computing system into multiple segmented core dies, where each core die contains a portion of the neural network layers. This segmentation allows independent optimization of each die and distributes the computational load. The control circuit on a separate logic die coordinates data flow between segmented dies, managing overall system complexity while enabling parallel processing to improve AI performance.
2Adaptability or versatility
If weights are stored in synapse arrays across multiple layers, then neural network capability is improved, but data transmission time and latency increase
Solution Approach 1:
The patent stores weights in synapse arrays distributed across multiple vertical layers in the 3D stacked architecture. This vertical distribution allows weights for different neural network layers to be physically closer in the vertical dimension, reducing transmission time compared to horizontal distribution in 2D. The TSVs enable rapid vertical data access, improving neural network capability while minimizing data transmission latency.
Solution Approach 2:
The control circuit pre-processes and prepares data before transmission to the synapse arrays, and pre-loads weights into the appropriate core dies before computation is needed. This preliminary action reduces the actual computation and transmission time during neural network operations, enabling complex multi-layer networks while minimizing latency.
3Power
If more core dies are stacked to handle complex calculations, then processing power is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the high-power neuromorphic processing across multiple identical or semi-identical core dies, each containing a standardized synapse array and neuron circuits. This modular segmentation allows each die to be manufactured using the same fabrication process, simplifying production. The standardized interfaces and TSV configurations enable automated assembly and testing, reducing manufacturing complexity while scaling processing power through increased die count.
Solution Approach 2:
Each core die is designed with universal functionality to handle multiple neural network operations (synaptic weight storage, neuron computation, data transmission). This multi-functionality reduces the variety of specialized components needed, simplifying the manufacturing process. The control circuit on the logic die provides universal coordination for all core dies, enabling scalable manufacturing without proportionally increasing system complexity.
Data Source
AI summary
A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.