3D Stacked Nonvolatile Memory Cell Architecture for Wafer Area Optimization
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Solution Overview
Problem
There is a challenge in increasing memory capacity within a given space in semiconductor devices, particularly in nonvolatile memory devices, where traditional floating gate field effect transistors face limitations in miniaturization and efficient use of wafer area.
Innovation Solution
The design incorporates a memory device with multiple gate structures and source/drain regions, including a first and second gate structure with a tunnel oxide, charge trap, and dielectric layers, and a doped control gate region, along with trench isolation and epitaxial growth of semiconductor layers to form a stack of patterns, enabling efficient use of space and fabrication of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional floating gate field effect transistors are used, then the device structure is simple and easy to manufacture, but the memory capacity per unit area is limited
Solution Approach 1:
The patent transitions from planar 2D memory cell architecture to a 3D stacked architecture where multiple gate structures are arranged vertically. The first gate structure is positioned below the second gate structure with source/drain regions connecting them, effectively utilizing the vertical dimension to increase storage density per unit wafer area.
Solution Approach 2:
The patent implements a nested configuration where the first gate structure is embedded within the substrate and the second gate structure is positioned above it, with source/drain regions nesting between them. This nested arrangement allows multiple functional elements to occupy overlapping spatial volumes, increasing effective density.
2Quantity of substance
If the size of memory cells is decreased to increase capacity, then more cells fit in given space, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory cell into multiple discrete functional segments: first gate structure, second gate structure, source regions, and drain regions. Each segment can be independently formed and controlled during fabrication, allowing precise dimensional control of individual components while maintaining overall cell density.
Solution Approach 2:
The patent employs selective doping with different impurity concentrations in different regions (first impurity concentration in source regions, second impurity concentration in drain regions). This local differentiation allows optimization of electrical properties in each region independently, facilitating precise control of cell characteristics despite miniaturization.
3Area of stationary object
If stackable cell architectures are employed, then wafer area utilization improves, but device complexity increases
Solution Approach 1:
The source and drain regions serve multiple functions simultaneously: they act as electrical contacts for both the first and second gate structures, provide current pathways between stacked gates, and serve as doping regions for charge injection. This multi-functionality reduces the need for additional dedicated structures, managing complexity while achieving stacking.
Solution Approach 2:
The patent merges the source/drain regions to serve both gate structures above and below, rather than providing separate source/drain contacts for each gate. This consolidation reduces the total number of discrete components and simplifies the fabrication process while maintaining the stacked architecture's density benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for increased memory capacity and efficient use of wafer area by forming stackable cell architectures, enhancing the performance and density of nonvolatile memory devices.
Implementation Method 1
a tunnel oxide layer on the channel, a floating gate (charge trap) layer on the tunnel oxide layer
Implementation Method 2
a charge trap layer surrounding the dielectric layer and the first elongate conductive gate electrode
Implementation Method 3
The first and second source/drain regions may include single crystal semiconductor regions
Data Source
AI summary
A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.