Stacked Nonvolatile Memory Device with Common Source Line Driver
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Solution Overview
Problem
As memory devices become more integrated and complex, existing technologies face challenges in efficiently packing a high number of memory cells while maintaining effective electrical connections and reducing chip size, leading to increased complexity and potential defects in wiring and source voltage distribution.
Innovation Solution
A nonvolatile memory device is designed with a cell-on-peri or cell-over-peri structure, featuring a stacked configuration where the memory cell array is located on top of peripheral circuits, utilizing a common source line driver and contact plugs to distribute voltage efficiently, reducing the need for common source plugs and minimizing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell sizes are decreased for high integration, then the capacity and degree of integration are improved, but the complexity of operation circuits and wirings increases
Solution Approach 1:
The patent transitions from planar memory cell arrangement to a three-dimensional stacked configuration where memory cell arrays are formed vertically on top of peripheral circuits. This vertical stacking in the third dimension (Z-axis) enables high integration without increasing lateral wiring complexity, as connections are established through vertical contact plugs rather than extensive lateral interconnections.
Solution Approach 2:
The memory device is segmented into distinct functional layers: peripheral circuits on the lower substrate and memory cell arrays on upper substrates. This segmentation allows independent optimization of each layer and reduces the complexity of interconnections by separating control functions from storage functions into different vertical levels.
2Quantity of substance
If the number of memory cells is increased, then the integration density is improved, but the chip size and wiring complexity increase
Solution Approach 1:
Multiple memory cell arrays are stacked vertically on top of each other using multiple upper substrates positioned at different heights. This three-dimensional stacking enables a large number of memory cells to be integrated within a small lateral footprint, dramatically increasing storage capacity without proportionally increasing chip area.
Solution Approach 2:
The structure implements a nested configuration where memory cell arrays are positioned on top of peripheral circuits, and multiple such stacks are arranged within the chip. This nesting approach maximizes space utilization by placing functional blocks in vertical layers rather than requiring lateral expansion.
3Reliability
If common source plugs are used for voltage distribution, then electrical connection is established, but the chip size and manufacturing complexity increase
Solution Approach 1:
The common source voltage distribution function is extracted from the traditional planar common source plug configuration and repositioned to the lower substrate level. The common source line driver is formed separately on the lower substrate and connects to the memory cell arrays through vertical contact plugs, eliminating the need for complex three-dimensional common source plug formation and simplifying the manufacturing process.
Data Source
AI summary
A nonvolatile memory device and a method of manufacturing the device, the device including a first semiconductor layer, the first semiconductor layer including an upper substrate, and a memory cell array, the memory cell array including a plurality of gate conductive layers stacked on the upper substrate and a plurality of pillars passing through the plurality of gate conductive layers and extending in a direction perpendicular to a top surface of the upper substrate; and a second semiconductor layer under the first semiconductor layer, the second semiconductor layer including a lower substrate, at least one contact plug between the lower substrate and the upper substrate, and a common source line driver on the lower substrate and configured to output a common source voltage for the plurality of pillars through the at least one contact plug.