Stacked Opto-Electronic Package Layout for Compact Interconnects
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Solution Overview
Problem
There is a need for opto-electronic integrated devices that provide improved performance and a more compact form factor to be implemented in smaller devices.
Innovation Solution
The integration of a substrate with an opto-electronic device and stacked integrated devices, utilizing solder and pillar interconnects, along with encapsulation layers, to create a compact package configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If integrated devices are arranged in a stacked configuration with vertical overlap, then the form factor is reduced and the package becomes more compact, but the manufacturing complexity increases due to multiple solder interconnect layers and alignment requirements
Solution Approach 1:
The patent transitions from a planar two-dimensional arrangement of integrated devices to a three-dimensional stacked configuration with vertical overlap. Multiple integrated devices are positioned at different heights above the substrate, connected through vertical solder interconnects. This dimensional change enables significantly reduced package footprint while accommodating multiple functional layers in the vertical dimension, directly resolving the contradiction between compactness and manufacturing complexity by exploiting the third dimension.
Solution Approach 2:
The patent implements a nested structure where multiple integrated devices are stacked vertically with each device positioned within the vertical projection envelope of the package. The first integrated device is coupled to the substrate, the second integrated device is coupled to the first device, and subsequent devices are coupled in sequence, creating a nested vertical arrangement. This nesting approach maximizes space utilization and achieves compact form factor while organizing complexity in a hierarchical manner.
2Reliability
If multiple integrated devices are stacked vertically with solder interconnects, then electrical paths between components are shortened and performance is improved, but the reliability requirements increase due to multiple interconnect interfaces
Solution Approach 1:
The patent merges multiple electrical connection functions into a unified stacked architecture. The substrate provides the base connection layer, the first integrated device provides intermediate connections, and the second integrated device provides upper-level connections, creating a consolidated vertical interconnect system. This merging of connection layers into a stacked configuration reduces the total path length for electrical signals compared to traditional planar routing, improving performance while managing reliability through standardized interconnect interfaces.
Solution Approach 2:
The patent moves electrical connections from a two-dimensional planar routing scheme to a three-dimensional vertical stacking scheme. Solder interconnects extend vertically between stacked integrated devices, creating direct electrical pathways through the z-dimension. This dimensional transition significantly shortens electrical paths between components that would otherwise require long lateral traces, improving signal integrity and performance while the modular vertical interface design manages the complexity of multiple connection points.
Data Source
AI summary
A device comprising a substrate; an opto-electronic integrated device coupled to the substrate; a first integrated device coupled to the substrate through a first plurality of solder interconnects; and a second integrated device coupled to the first integrated device through a second plurality of solder interconnects.