Stacked Optoelectronic Package Layout for Shorter Signal Paths
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Solution Overview
Problem
Current optoelectronic packages with horizontal arrangements of ASIC and photonics engines on PCBs require large device areas, leading to decreased yield and long electrical paths, which hinder high-speed transmission and increase thermal accumulation.
Innovation Solution
The optoelectronic package design features a carrier with a protrusion portion for power supply and a recessed area for optoelectronic devices, eliminating through-silicon vias and using conductive bumps and redistribution layers for electrical connections, allowing for a stacked structure that reduces device area and electrical path length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If optoelectronic devices and ASIC are arranged in a horizontal direction on PCB, then electrical connection can be established, but device area increases and yield decreases
Solution Approach 1:
The patent transitions from a horizontal 2D arrangement of optoelectronic devices and ASIC on PCB to a vertical 3D stacked architecture. The optoelectronic devices are positioned above the ASIC through a substrate, with electrical connections established via through-silicon vias (TSVs) and conductive bumps. This dimensional change reduces the device area footprint while maintaining electrical connectivity.
2Reliability
If optoelectronic devices and ASIC are arranged in a horizontal direction, then connection can be made, but electrical path length increases
Solution Approach 1:
The electrical connection path is shortened by transitioning from a horizontal routing path through PCB layers to a vertical path through the substrate using TSVs and conductive bumps. The ASIC connects to optoelectronic devices through direct vertical interconnections, eliminating long horizontal traces and reducing signal transmission distance.
3Productivity
If horizontal arrangement is used, then device integration is achieved, but thermal accumulation increases
Solution Approach 1:
The vertical stacked architecture improves thermal management by enabling heat dissipation in the vertical direction through the substrate and packaging structure. Thermal paths are optimized by conducting heat away from the optoelectronic devices and ASIC through the substrate to heat sink structures, reducing thermal accumulation compared to horizontal arrangements where heat must dissipate laterally.
Data Source
AI summary
An optoelectronic package and a method of manufacturing an optoelectronic package are provided. The optoelectronic package includes a carrier. The carrier includes a first region and a second region. The first region is configured to supply power to a processing unit disposed on the carrier. The second region is for accommodating at least one optoelectronic device electrically coupled to the processing unit.