Stacked OS Transistor Memory for Product-Sum Operations
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently reading and performing product-sum operations on weight coefficients for neural networks, particularly in image recognition tasks, where higher speed and reduced chip area are required.
Innovation Solution
A semiconductor device is designed with a product-sum operation circuit and memory device, featuring a stacked structure of transistors, including a metal oxide transistor in the channel formation region, which enables efficient reading of weight coefficients and reduced chip area by utilizing a combination of Si transistors and OS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional processor (CPU/GPU) is used for neural network calculations, then the device can perform product-sum operations, but the processing speed and efficiency are insufficient for high-performance image recognition tasks
Solution Approach 1:
The device is divided into two distinct layers: a first layer with transistors formed on a semiconductor substrate for control functions, and a second layer with oxide semiconductor transistors for memory and data retention functions. This segmentation allows each layer to be optimized for its specific function, enabling high-speed processing while maintaining calculation accuracy through specialized transistor characteristics in each region.
2Area of stationary object
If the chip area is reduced by integrating memory and processing circuits, then the device density increases, but the complexity of reading weight coefficients and performing operations increases
Solution Approach 1:
The patent merges the memory circuit and product-sum operation circuit into a single integrated device structure. The first circuit layer handles control and operation functions while the second layer handles memory functions, allowing weight coefficients to be stored and processed in close proximity. This merging reduces the distance for data transfer and eliminates the need for separate memory chips, thereby reducing overall chip area while managing complexity through functional layering.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked structure. By forming the second layer of oxide semiconductor transistors above the first layer on the semiconductor substrate, the design utilizes the vertical dimension to separate memory and processing functions. This dimensional change allows both functions to coexist in a compact footprint without excessive interconnection complexity, as vertical stacking reduces the number of inter-layer connections compared to lateral integration.
3Duration of action of stationary object
If oxide semiconductor transistors are used in the memory cell, then data retention time increases due to low off-state current, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies local quality by using oxide semiconductor transistors specifically in the memory cell region (second layer) where low off-state current and long data retention are critical, while the control and operation circuits (first layer) use conventional transistors formed on the semiconductor substrate. This localized application of oxide semiconductor technology provides the necessary data retention characteristics in the memory region without requiring the entire device to be manufactured with oxide semiconductor processes, thereby reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device efficiently performs product-sum operations and reduces chip area by leveraging the low off-state current of OS transistors, ensuring reliable data retention and high processing speed.
Implementation Method 1
The drain current of the OS transistor in an off state (such a current is also referred to as an off-state current) is extremely low; thus, when the OS transistor is used in a memory cell of a DRAM, electric charge accumulated in a capacitive element can be retained for a long time.
Data Source
AI summary
A semiconductor device which can efficiently perform reading of a weight coefficient and a product-sum operation is provided. The semiconductor device includes a product-sum operation circuit and a memory device. The product-sum operation circuit is formed using transistors formed on a semiconductor substrate, and a memory cell of the memory device is formed using an OS transistor provided to be stacked above the semiconductor substrate. The semiconductor device includes a plurality of product-sum operation units where the product-sum operation circuit and the memory cell of the memory device are electrically connected to each other. In each of the product-sum operation units, a weight coefficient stored in the memory cell can be read and a product-sum operation can be performed.