Stacked Oxide Switching Transistor Layout for DCDC Converter Heat Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DCDC converters face challenges in high integration due to large area occupation by switching transistors, leading to increased cost and heat generation issues, which hinder circuit integration and efficiency.
Innovation Solution
The solution involves stacking a switching transistor with a backgate connected to a substrate over a controller circuit, using an oxide semiconductor transistor with a backgate for heat dissipation and reducing off-state current, and incorporating a potential hold portion with an oxide semiconductor transistor and capacitor to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the switching transistor is formed over the semiconductor chip, then the circuit integration is improved, but the area occupied by the switching transistor becomes large (10% to 50% of the chip area)
Solution Approach 1:
The patent applies three-dimensional stacking to place the switching transistor vertically over the controller circuit, transitioning from a planar two-dimensional layout to a three-dimensional structure. This dimensional change allows the switching transistor to occupy minimal chip area while maintaining full functionality, resolving the contradiction between circuit integration and area occupation.
2Area of moving object
If high integration is achieved by stacking components, then the chip area is reduced, but heat generation problems occur
Solution Approach 1:
The patent introduces a backgate as an intermediary thermal management structure between the oxide semiconductor layer and the substrate. The backgate serves as a heat dissipation pathway, conducting heat away from the stacked components to the substrate, thereby enabling high integration while controlling temperature rise.
3Power
If a conventional silicon transistor is used as the switching transistor, then the channel width can be increased for higher power handling, but the off-state current becomes large
Solution Approach 1:
The patent changes the material parameter of the transistor channel from conventional silicon to oxide semiconductor. This material parameter change fundamentally alters the electrical characteristics, enabling extremely low off-state current even when the channel width is increased for higher power handling capability, thus resolving the contradiction between power handling and energy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a highly integrated semiconductor device with reduced area per chip, increased chip density, and effective heat management, while lowering power consumption and maintaining performance by intermittently stopping current supply to bias circuits.
Implementation Method 1
heat generated by an oxide semiconductor layer can be absorbed and released to a substrate
Implementation Method 2
a transistor in which a channel contains a wide bandgap semiconductor material such as an oxide semiconductor
Data Source
AI summary
To increase the degree of integration of a semiconductor device such as a DCDC converter. In a semiconductor device (e.g., DCDC converter) including a controller circuit and a switching transistor, the switching transistor formed using an oxide semiconductor layer is stacked over a substrate on which the controller circuit is formed. The switching transistor includes a backgate to release heat generated in the oxide semiconductor layer. The backgate has electrical conduction with a wiring to release heat and prevent a temperature increase with integration. Moreover, for power saving, a potential hold portion including a transistor and a capacitor may be formed using part of the oxide semiconductor layer over the controller circuit. The potential hold portion is formed in a circuit for generating a bias potential in the controller circuit.