Semiconductor package
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for compact, high-performance semiconductor packages with improved thermal radiation and electrical properties is challenging due to the need for reduced size and weight, as well as the complexity of stacking multiple semiconductor chips, which often results in reliability issues with electrical connections.
Innovation Solution
A semiconductor package design featuring a first semiconductor die with a semiconductor substrate, wiring layer, redistribution patterns, and passivation layers, including a silicon nitride and silicon oxide layer, which allows for efficient thermal dissipation and compact size, along with a second semiconductor die mounted on pads with a molding layer and external terminals for enhanced electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of semiconductor chips is increased in a stacked package, then the functional performance is improved, but the reliability of electrical connections deteriorates
Solution Approach 1:
The package is divided into multiple semiconductor chips (first, second, and third chips) stacked vertically, with each chip containing divided circuits. This segmentation allows functional performance to be improved through parallel processing while maintaining connection reliability by distributing electrical connections across multiple independent pads and interconnect structures.
Solution Approach 2:
The patent transitions from planar packaging to three-dimensional stacked packaging, arranging multiple semiconductor chips vertically along the thickness direction. This dimensional change enables increased functional performance within a compact footprint while managing electrical connection reliability through vertical interconnect structures including pads, bumps, and wire bonds.
2Volume of moving object
If the size of semiconductor devices is reduced, then the compactness is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent achieves compactness by stacking multiple semiconductor chips vertically in the thickness direction rather than arranging them horizontally. This dimensional transition reduces the planar footprint significantly while the electrode terminals are arranged in a grid pattern on each chip surface, allowing precise alignment through standardized bump and wire bond structures.
Solution Approach 2:
Multiple semiconductor chips are nested vertically one above another in the thickness direction, with each chip containing complete functional circuits. This nesting approach achieves high compactness by utilizing the vertical dimension, while the electrode terminal pitch is managed through standardized pad layouts and interconnect structures on each chip surface.
3Reliability
If the passivation layer thickness is increased, then the electrical insulation is improved, but the thermal radiation performance deteriorates
Solution Approach 1:
The patent applies passivation layers with different thicknesses in different regions: a first passivation layer with thickness of 0.3-0.5 times the redistribution pattern thickness for electrical insulation, and a second passivation layer with smaller thickness for thermal radiation. This local quality differentiation optimizes both electrical insulation and thermal performance in their respective regions.
Solution Approach 2:
The patent optimizes passivation layer thickness as a critical parameter, setting the first passivation layer thickness to 0.3-0.5 times the redistribution pattern thickness and the second passivation layer thickness to be smaller than the redistribution pattern thickness. These parameter changes balance electrical insulation requirements with thermal radiation performance.
Data Source
AI summary
A semiconductor package is provided that includes: a first semiconductor die, and a second semiconductor die on the first semiconductor die. The first semiconductor die includes a semiconductor substrate, a wiring layer on an active surface of the semiconductor substrate, a redistribution pattern on an inactive surface of the semiconductor substrate, a first passivation layer on the inactive surface of the semiconductor substrate wherein the first passivation layer is on the redistribution pattern and has an opening that exposes a top surface of the redistribution pattern, and a backside pad on the first passivation layer and coupled through the opening to the redistribution pattern. An inner lateral surface of the opening is inclined at an angle of 90 to 105 degrees relative to the top surface of the redistribution pattern. A thickness of the first passivation layer is 0.3 to 0.5 times a thickness of the redistribution pattern.