Stacked Semiconductor Package with Backside Power Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrating multiple types of devices or components in integrated circuits and packages faces challenges in optimizing electrical connections and thermal designs, particularly in reducing signal interaction latency and energy loss, while minimizing the distance between components and enhancing design flexibility.
Innovation Solution
The solution involves forming a die stack structure with reduced thickness and horizontal spacing between semiconductor substrates, utilizing through vias and power distribution networks on the backside of wafers, and employing dielectric-to-dielectric and metal-to-metal bonding techniques to connect conductive pads, along with interconnect structures that facilitate efficient power and ground signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct metallization structure formation or metal to metal jointing is used for electrical connection between components, then electrical connection is established, but signal interaction latency increases and energy loss occurs
Solution Approach 1:
The patent transitions from planar electrical connections to three-dimensional vertical connections through stacked semiconductor dies connected by conductive vias. This dimensional change reduces signal path length by enabling direct vertical routing between components on adjacent dies, thereby reducing signal interaction latency while maintaining reliable electrical connection.
Solution Approach 2:
The patent implements nested interconnect structures where conductive vias are formed within semiconductor dies and extend through multiple layers. The vias are nested within the die structure, allowing electrical connections to be embedded within the three-dimensional stack rather than requiring external metal jointing, thus reducing signal latency.
2Adaptability or versatility
If multiple types of devices or components are integrated, then system functionality is enhanced, but design complexity increases
Solution Approach 1:
The patent employs standardized interconnect structures including conductive vias, dielectric layers, and bonding interfaces that serve multiple functions across different device types. These universal interconnect elements enable diverse semiconductor devices (logic, memory, sensors) to be integrated in a stacked configuration using the same fabrication processes, thereby enhancing system functionality without proportionally increasing design complexity.
Solution Approach 2:
The patent divides the integrated system into separate semiconductor dies that can be independently designed, fabricated, and tested. Each die contains specific functional components, and the segmentation allows parallel development of different device types while using standardized interconnect structures for integration, thus managing design complexity through modular architecture.
3Loss of time
If component spacing is reduced to minimize distance, then signal latency decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the spatial parameters of component arrangement by transitioning from lateral placement to vertical stacking. The component spacing in the vertical dimension can be controlled through precise deposition thicknesses of dielectric and conductive layers during fabrication, allowing reduced effective distance between components while maintaining manufacturable precision through layer-by-layer process control rather than requiring high-precision lateral positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces signal latency and energy loss, enhances design flexibility, and optimizes electrical connections by providing a more efficient power distribution network, thereby improving the overall performance of integrated circuits and packages.
Implementation Method 1
first dielectric layers 112a stacked on the first semiconductor substrate 103a with first interconnect wirings 122a embedded in the first dielectric layers 112a
Implementation Method 2
first conductive vias 125a embedded in the first dielectric layers 112a
Implementation Method 3
metal-to-metal bonding
Data Source
AI summary
A semiconductor package structure and a manufacturing method thereof is provided. The semiconductor package includes a first semiconductor die, including a semiconductor substrate and a first interconnect structure disposed on the semiconductor substrate; a second semiconductor die disposed on and electrically connected to the first semiconductor die, including a second semiconductor substrate and a second interconnect structure; a third interconnect structure, where in the second interconnect structure and the third interconnect structure are disposed on opposite sides of the second semiconductor substrate, and wherein the second interconnect structure is between the first interconnect structure and the third interconnect structure.