Stacked Semiconductor Package With Minimized Chip Gap
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Solution Overview
Problem
There is a need for semiconductor packages with reduced thickness to achieve miniaturization and weight reduction in electronic components while maintaining high-capacity data processing capabilities.
Innovation Solution
A semiconductor package design featuring a stacked chip structure with a first semiconductor chip and a second semiconductor chip, where the upper pad structure of the first chip is electrically connected to the lower bonding pads and connection pad patterns of the second chip through connection wirings, allowing for minimized gap and enhanced electrical connectivity between the chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are combined in a stacked structure to reduce package volume, then the package thickness is reduced, but the gap between chips increases making electrical connection difficult
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional stacked arrangement, allowing chips to be positioned vertically one above another. This dimensional change enables reduced package footprint while maintaining electrical connectivity through vertical vias that penetrate through the chips and interpose substrate, solving the gap problem inherent in stacked configurations.
Solution Approach 2:
The patent introduces an interpose substrate as an intermediary component between the lower and upper chips. This mediator provides a platform with through-vias that electrically connect bonding pads on the lower chip surface to bonding pads on the upper chip surface, enabling reliable electrical connection despite the vertical separation and gap between stacked chips.
2Volume of moving object
If chips are stacked to achieve miniaturization, then package size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor package into distinct modular segments: lower chip, interpose substrate, and upper chip, each with specific functions. This segmentation allows independent fabrication and testing of each component before assembly, simplifying the overall manufacturing process despite the three-dimensional configuration, and enabling standardized production of each module.
3Reliability
If through-electrodes penetrate the first chip to connect to the second chip, then electrical connectivity is improved, but the first chip is damaged
Solution Approach 1:
The interpose substrate serves as a mediator that receives through-electrodes from the lower chip without compromising the lower chip's integrity. The through-vias in the interpose substrate provide the necessary electrical connection path to the upper chip, distributing the mechanical and electrical stress away from the delicate chip structures and protecting them from damage.
Data Source
AI summary
A semiconductor package comprising a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip includes a first semiconductor body, an upper pad structure, and a first through-electrode penetrating the first semiconductor body and electrically connected to the upper pad structure, and the second semiconductor chip includes a second semiconductor body, a lower bonding pad, and an internal circuit structure including a circuit element, internal circuit wirings, and a connection pad pattern disposed on the same level as the lower bonding pad, the upper pad structure includes upper bonding pads and connection wirings, the upper bonding pads are disposed at positions corresponding to the lower bonding pad and the connection pad pattern, and the internal circuit structure is electrically connected to the first through-electrode through at least one of the upper bonding pads and the connection wirings.