Stacked Semiconductor Package Layout for Compact Chip Integration

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Solution Overview

Problem

There is a need for smaller and more compact semiconductor packages to meet the demand for smaller electronic products, as existing semiconductor packages are not optimized for reduced size without compromising performance.

Innovation Solution

A method of fabricating a semiconductor package that involves preparing a panel package with a redistribution substrate, connection substrate, and lower semiconductor chips, sawing it into strip packages, and then adding upper semiconductor chips with direct electrical connections, along with a molding layer to create a compact and efficient package structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If traditional semiconductor package structures are used, then electrical connectivity is maintained, but package size cannot be reduced

Engineering Contradiction:

Improvepackage sizeVSAvoidelectrical connectivity

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The patent transitions from planar electrical connections to three-dimensional vertical connections by stacking upper semiconductor chips above lower semiconductor chips with direct electrical contact between chip surfaces, eliminating the need for lateral bonding wires or bumps and enabling compact package sizing

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If package size is reduced, then compactness is improved, but fabrication complexity increases

Engineering Contradiction:

Improvepackage sizeVSAvoidfabrication process complexity

Core Design Contradiction:

Volume of moving objectVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by pre-forming connection substrates with conductive structures, pre-mounting lower semiconductor chips, and pre-establishing electrical connection patterns before the final chip stacking and molding operations, thereby simplifying the overall fabrication process despite the three-dimensional architecture

Inventive Principle:

Principle #10Preliminary action

3Reliability

If direct electrical connections between chips are implemented, then electrical connectivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveelectrical connectivityVSAvoidchip alignment precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces connection substrates with conductive structures as intermediary elements between upper and lower semiconductor chips, providing alignment features and connection pathways that tolerate minor positioning variations while ensuring reliable electrical connectivity

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11791321B2Method of fabricating semiconductor package and semiconductor package

Publication Date: 2023.10.17 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.