Stacked Semiconductor Package Layout for Compact Multi-Chip Reliability
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving miniaturization and high capacity while maintaining structural reliability and electrical connectivity between multiple semiconductor chips.
Innovation Solution
A semiconductor package design featuring a package redistribution layer, cover insulating layer, lower and upper semiconductor chips, connection posts, and molding layers, with specific electrical connections and offsets to minimize horizontal area and enhance structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked vertically to increase capacity, then the package capacity and functionality are improved, but the structural reliability and electrical connectivity between chips become more difficult to maintain
Solution Approach 1:
The patent implements a stacked chip structure where multiple semiconductor chips are vertically arranged and nested within a single package. The lower semiconductor chip is positioned below the upper semiconductor chip, with connection posts extending through intermediate layers to establish electrical connections between stacked chips. This nesting approach increases package capacity while maintaining structural integrity through the unified package structure.
Solution Approach 2:
The patent transitions from a planar arrangement of chips to a three-dimensional stacked configuration. By arranging chips vertically in the thickness direction rather than side-by-side in the horizontal plane, the package achieves higher capacity within a smaller footprint. Connection posts extend vertically through intermediate layers to maintain electrical connectivity in this multi-dimensional structure.
2Volume of moving object
If multiple semiconductor chips are stacked vertically to miniaturize the package, then the package volume is reduced, but the electrical connectivity and structural integrity between chips become more difficult to maintain
Solution Approach 1:
The patent reduces package volume by stacking chips vertically in the thickness direction rather than arranging them horizontally. This three-dimensional configuration minimizes the package footprint while maintaining functional capacity. Connection posts extend vertically through intermediate layers to establish electrical connections, simplifying the interconnect structure compared to horizontal routing.
Solution Approach 2:
The patent divides the package into distinct functional layers: a lower semiconductor chip, an upper semiconductor chip, intermediate layers including cover insulating layers and molding layers, and connection posts for electrical interconnection. This segmentation allows each layer to be optimized independently while maintaining overall structural integrity and electrical connectivity in the compact stacked configuration.
3Ease of manufacture
If connection posts are placed adjacent to the semiconductor chip to simplify manufacturing, then the manufacturing process is simplified, but the horizontal area of the package increases
Solution Approach 1:
The patent positions connection posts in the vertical dimension, extending from the lower semiconductor chip through intermediate layers to the upper semiconductor chip. This vertical arrangement of connection posts eliminates the need for extensive horizontal routing, thereby simplifying the manufacturing process while maintaining a compact horizontal footprint.
Solution Approach 2:
The connection posts are nested within the vertical stack, extending through the intermediate layers between the lower and upper semiconductor chips. This nested configuration allows electrical connections to be established vertically within the compact package structure, avoiding horizontal expansion and simplifying the manufacturing process.
Data Source
AI summary
A semiconductor package including a package redistribution layer, a cover insulating layer on the package redistribution layer; a lower semiconductor chip arranged between the package redistribution layer and the cover insulating layer and electrically connected to the package redistribution layer, a lower molding layer surrounding the lower semiconductor chip and filling between the package redistribution layer and the cover insulating layer, a plurality of connection posts electrically connected to the package redistribution layer by passing through the cover insulating layer and the lower molding layer, an upper semiconductor chip arranged above the cover insulating layer electrically connected to the plurality of connection posts, and an upper molding layer filling between the upper semiconductor chip and the cover insulating layer and surrounding the upper semiconductor chip may be provided.