Stacked Semiconductor Package Layout for Corner Stress Relief
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving reduced size and weight while maintaining structural stability and electrical connectivity, particularly in stacked configurations.
Innovation Solution
A semiconductor package design featuring alternatingly stacked semiconductor chips with specific pad arrangements and bonding wire connections, minimizing pressure on chip corners during fabrication to enhance structural stability and reduce failure occurrences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are stacked to reduce size and weight, then device integration is improved, but structural stability deteriorates due to pressure on chip corners
Solution Approach 1:
The patent applies asymmetry by intentionally designing alternating protrusion and recess configurations in the stacked semiconductor chips. Specifically, odd-numbered chips protrude in a first direction while even-numbered chips protrude in a second direction, creating an asymmetric alternating pattern that distributes mechanical stress away from chip corners during the bonding process, thereby maintaining structural stability while achieving compact packaging.
2Reliability
If bonding wires are used to connect pads, then electrical connectivity is improved, but fabrication failure increases due to pressure on chip corners
Solution Approach 1:
The patent implements preliminary anti-action by pre-configuring the alternating protrusion and recess structure before the bonding wire connection process. This pre-arranged asymmetric configuration proactively counteracts the harmful pressure that would otherwise be applied to chip corners during wire bonding, preventing fabrication failures before they occur while enabling reliable electrical connectivity through the bonding wires.
3Stability of the object's composition
If chips are stacked in alternating directions, then structural stability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the stacked chip structure into distinct alternating units where odd-numbered chips have one protrusion configuration and even-numbered chips have another. This segmentation into repeating asymmetric units simplifies the overall design methodology while achieving structural stability, as each segment follows the same alternating pattern rather than requiring unique configurations for each chip.
Data Source
AI summary
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises semiconductor chips stacked on a substrate and including first and second pads on top surfaces thereof, and bonding wires connecting the first and second pads to the substrate. The semiconductor chips alternately protrude in a first direction and its opposite direction. The semiconductor chip has a first lateral surface spaced apart from another semiconductor chip. The top surface of the semiconductor chip is provided thereon with a first arrangement line extending along the first lateral surface and with second arrangement lines extending from opposite ends of the first arrangement line. Wherein as a distance between the first and second arrangement lines increases, a distance between the second arrangement lines and the first lateral surface increases. The first pads are arranged along the first arrangement line. The second pads are arranged along the second arrangement lines.