Semiconductor package
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Solution Overview
Problem
Existing semiconductor packages face challenges in efficiently integrating multiple semiconductor chips while maintaining compact size and effective heat dissipation, particularly when high heat-generating chips are included.
Innovation Solution
A semiconductor package design featuring a lower package with a first redistribution structure and a conductive redistribution pattern, including a redistribution device, which includes a redistribution structure comprising a first semiconductor chip, a first semiconductor chip, a second semiconductor chip, a second semiconductor chip, a molding layer and a conductive redistribution structure comprising a first redistribution structure and a conductive redistribution structure, a second redistribution structure, a second semiconductor chip, a molding layer, and a conductive post, with the upper package vertically overlapping with the second mounting region but not covering the first semiconductor chip, and a heat dissipation plate to manage heat.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated in a compact package, then device functionality and capacity are improved, but heat dissipation becomes more difficult
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional stacking, where chips are arranged vertically across multiple layers (first layer, second layer, third layer) connected by conductive posts. This dimensional change increases functional capacity while managing heat through vertical spacing and heat dissipation structures positioned at the top surface.
Solution Approach 2:
The patent introduces heat dissipation structures (heat dissipation members) as intermediary elements between the stacked chips and the external environment. These structures are positioned at the top surface of the package and serve as mediators to conduct and dissipate heat generated by the chips, addressing the thermal management challenge of compact multi-chip integration.
2Volume of moving object
If multiple semiconductor chips are stacked vertically, then space utilization is improved, but electrical connectivity between chips becomes more complex
Solution Approach 1:
The conductive posts serve multiple functions: they provide mechanical support to hold chips in vertical stacking, establish electrical connectivity between chips across layers, and enable signal transmission. This multi-functionality simplifies the overall structure compared to having separate mechanical and electrical connection systems.
Solution Approach 2:
The patent extracts the electrical connection function from the chip surfaces and relocates it to dedicated conductive posts positioned between chips. This separation allows chips to be connected vertically through discrete conductive elements rather than requiring complex inter-chip wiring on chip surfaces, simplifying the electrical connectivity architecture.
3Ease of manufacture
If chips are mounted side-by-side on a package substrate, then manufacturing is simplified, but heat dissipation efficiency decreases
Solution Approach 1:
The patent transitions from two-dimensional side-by-side chip mounting to three-dimensional vertical stacking. This dimensional change increases the surface area available for heat dissipation at the top of the package while maintaining compact footprint, and allows heat dissipation structures to be positioned optimally for thermal management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design allows for improved heat dissipation and efficient integration of multiple semiconductor chips, preventing heat-related degradation of surrounding components and enhancing overall package performance.
Implementation Method 1
a conductive post on the second mounting region of the first redistribution structure, the conductive post passing through the molding layer and being electrically connected to the first semiconductor chip through the first redistribution pattern of the first redistribution structure
Implementation Method 2
a heat dissipation plate attached to a top surface of the first semiconductor chip
Implementation Method 3
a heat dissipation plate attached to a top surface of the first semiconductor chip
Data Source
AI summary
A semiconductor package includes a lower package, an upper package on the lower package, and an inter-package connector between the lower package and the upper package. The lower package includes a first redistribution structure, a first semiconductor chip mounted on a first mounting region of the first redistribution structure, a second semiconductor chip mounted on a second mounting region of the first redistribution structure, a molding layer on the first redistribution structure and in contact with a side wall of the first semiconductor chip and a side wall of the second semiconductor chip, and a conductive post passing through the molding layer and electrically connected to the first semiconductor chip through a first redistribution pattern of the first redistribution structure. The upper package is on the molding layer, vertically overlaps with the second mounting region of the first redistribution structure, and does not cover the first semiconductor chip.