3D Stacked Semiconductor Package with Integrated ECC and FBI
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Solution Overview
Problem
Current semiconductor packages face challenges in increasing storage capacity while maintaining a thin and light design, and in improving data processing performance while reducing power consumption.
Innovation Solution
A semiconductor package is designed with a first bonding semiconductor chip that includes an error correction code (ECC) circuit and a frequency boosting interface (FBI) circuit, which is bonded with a second bonding semiconductor chip, allowing for efficient data processing and error correction without the need for separate ECC and FBI semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate ECC and FBI semiconductor chips are used, then error correction and frequency boosting functions are reliable, but the semiconductor package becomes thick and heavy
Solution Approach 1:
The patent combines the ECC circuit and FBI circuit into a single first bonding semiconductor chip. The first active layer includes both the error correction code circuit and the frequency boosting interface circuit, eliminating the need for separate chips and reducing overall package thickness.
Solution Approach 2:
The first bonding semiconductor chip is designed to perform multiple functions simultaneously - it includes both error correction capabilities (ECC circuit) and frequency boosting capabilities (FBI circuit). This multi-functional integration allows a single chip to replace what would traditionally require multiple separate chips.
2Reliability
If multiple separate semiconductor chips are used for different functions, then functional reliability is improved, but manufacturing complexity and assembly difficulty increase
Solution Approach 1:
The patent merges the ECC chip and FBI chip into a single integrated first bonding semiconductor chip. This reduces the number of bonding steps from multiple chip-to-chip bonding operations to a single bonding structure, simplifying the manufacturing process and reducing assembly complexity.
3Reliability
If traditional wire bonding methods are used for multiple chips, then electrical connections are reliable, but the package size increases and power consumption increases
Solution Approach 1:
The patent transitions from traditional planar wire bonding to a three-dimensional stacked architecture. The first bonding semiconductor chip is bonded to the second bonding semiconductor chip in the vertical direction, with penetration electrodes extending through the stack. This vertical integration reduces the horizontal footprint and overall package area while maintaining reliable electrical connections.
Data Source
AI summary
A semiconductor package includes: a semiconductor structure including: a first bonding semiconductor chip; a second bonding semiconductor chip on the first bonding semiconductor chip, the second bonding semiconductor chip having a cross-section area in a horizontal direction less than a cross-section area of the first bonding semiconductor chip in the horizontal direction; a chip connection pad between the first bonding semiconductor chip and the second bonding semiconductor chip; and a wire bonding pad on the first bonding semiconductor chip to be outside of the second bonding semiconductor chip; a first stacked semiconductor chip on the semiconductor structure and including a first chip pad on an upper surface thereof; and a second stacked semiconductor chip on the first stacked semiconductor chip to expose the first chip pad and including a second chip pad on an upper surface thereof.