Stacked Semiconductor Package With Integrated Leadframe Interconnects
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Solution Overview
Problem
Conventional semiconductor package assemblies face challenges in achieving high packaging density while maintaining reliability and electrical performance, as side-by-side chip arrangements result in larger package sizes and stacked assemblies with bonding wires lead to complex processes and potential interference.
Innovation Solution
A package assembly with a leadframe having multiple levels of electronic devices, where interconnects are formed integrally with leads to electrically couple different levels, reducing the need for bonding wires and improving electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If semiconductor chips are arranged side by side on a leadframe, then the package assembly can be manufactured with simple process, but the package size becomes larger than the sum of footprints of the semiconductor chips
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side chip arrangement to a three-dimensional stacked arrangement. Multiple semiconductor chips are vertically stacked on the leadframe, utilizing the vertical dimension to reduce the horizontal footprint of the package assembly while maintaining manufacturing feasibility through adapted bonding processes.
2Area of stationary object
If semiconductor chips are stacked and electrically coupled by bonding wires, then the package footprint is reduced, but the bonding process becomes complex and manufacture cost increases
Solution Approach 1:
The patent merges the electrical connection function with the mechanical support structure by integrating conductive leads directly into the leadframe. This eliminates the need for separate bonding wire operations, simplifying the manufacturing process while maintaining the compact stacked arrangement of semiconductor chips.
Solution Approach 2:
The patent extracts the bonding wire operation from the packaging process entirely. By using integrated leadframe leads that directly contact the semiconductor chips, the complex wire bonding step is removed, reducing process complexity and manufacturing cost while achieving the same electrical interconnection function.
3Area of stationary object
If bonding wires are used to electrically couple upper level chips to the leadframe, then the package assembly can be stacked to reduce footprint, but wire interference deteriorates high-frequency performance and reliability
Solution Approach 1:
The patent removes bonding wires from the package assembly by using direct leadframe leads for electrical connection. This extraction eliminates wire interference issues that degrade high-frequency performance and causes reliability problems from poor electrical contact, while maintaining the compact stacked configuration.
Solution Approach 2:
The patent replaces the mechanical wire bonding system with a rigid leadframe-based electrical connection system. The leadframe leads provide direct, stable electrical pathways from the semiconductor chips to the package exterior, eliminating the mechanical vulnerabilities and interference issues associated with flexible bonding wires.
Data Source
AI summary
A package assembly and a method for manufacturing the same are disclosed. The package assembly includes a leadframe having at least two groups of leads and a plurality of electronic devices arranged in at least two levels. Each group of leads is electrically coupled to a respective level of electronic devices. The package assembly further includes an interconnect for coupling one or more leads of one group of leads to one or more leads of another group of leads. The package assembly results in increased packaging density, less usage of bonding wires in the package assembly, improves reliability, and prevents possible interference.