Stacked Semiconductor Package With Vertical Porous Cooling Channels
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Solution Overview
Problem
The challenge is to enhance the heat-dissipating performance of semiconductor packages as they become thinner and more densely packed with semiconductor chips, while maintaining efficient operation and heat management.
Innovation Solution
A semiconductor package design incorporating vertical and horizontal porous structures with cooling channels and a cooling fluid system to facilitate efficient heat dissipation through multiple channels, allowing for the circulation of a cooling fluid to dissipate heat effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked in a multi-chip package to increase storage capacity, then the storage capacity increases, but the heat dissipation becomes more difficult due to increased thermal density
Solution Approach 1:
The patent introduces vertical cooling channels that extend through the multi-chip package in the thickness direction, transitioning from traditional planar heat dissipation to three-dimensional heat management. This allows cooling fluid to access heat sources from multiple levels simultaneously, effectively dissipating heat from stacked chips without increasing package footprint.
Solution Approach 2:
The patent employs a porous structure filled with phase change material within the cooling channels. This porous configuration increases the surface area for heat transfer and allows the phase change material to effectively absorb heat from multiple directions, enhancing heat dissipation capacity while maintaining compact dimensions.
2Length of stationary object
If the package thickness is reduced to decrease package size, then the package size decreases, but the heat dissipation performance deteriorates due to limited space for heat management structures
Solution Approach 1:
The patent embeds the cooling channels and phase change material within the existing multi-chip package structure, nesting the heat management system inside the package rather than adding external cooling components. This allows effective heat dissipation to be achieved without significantly increasing package thickness.
Solution Approach 2:
The patent utilizes a cooling fluid circulation system with cooling holes and channels that allow liquid coolant to flow through the package, providing active heat removal. The hydraulic cooling system efficiently transfers heat from the chips to the coolant, maintaining heat dissipation performance in thin packages.
3Temperature
If multiple cooling channels are introduced to improve heat dissipation, then the heat dissipation performance improves, but the device complexity increases due to additional structural components
Solution Approach 1:
The patent combines multiple cooling channels into a unified structure that serves the entire multi-chip package. The cooling channels are integrated with the package substrate and interconnect layers, merging the cooling function with the existing structural elements rather than adding separate, independent cooling components for each chip.
Solution Approach 2:
The cooling channels and phase change material serve multiple functions simultaneously: they provide thermal management for multiple chips, acts as structural support, and enable both liquid cooling and phase change heat absorption. This multi-functionality reduces the need for additional dedicated cooling components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly enhances the heat-dissipating performance of semiconductor packages by efficiently cooling multiple stacked chips, maintaining their operational efficiency and reducing thermal stress.
Implementation Method 1
a cooling fluid provided to the plurality of cooling holes of the vertical porous structure to flow inside the plurality of vertical cooling channels
Implementation Method 2
a vertical porous structure filling spaces of a plurality of vertical cooling channels passing through the first semiconductor chip, the second semiconductor chip, and the first underfill layer
Data Source
AI summary
A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, a chip connection terminal configured to electrically connect the first semiconductor chip to the second semiconductor chip, an underfill layer disposed between the first semiconductor chip and the second semiconductor chip and surrounding the chip connection terminal, a vertical porous structure filling spaces of a plurality of vertical cooling channels passing through the first semiconductor chip, the second semiconductor chip, and the underfill layer in a vertical direction, and having a plurality of cooling holes, and a cooling fluid provided to the plurality of cooling holes of the vertical porous structure to flow inside the plurality of vertical cooling channels.