Stacked Semiconductor Package With Rear-Side Power Vias
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high performance, high capacity, and miniaturization due to increased voltage drop and switching time caused by congested power wiring on the chip surface.
Innovation Solution
The semiconductor package design includes a stacked configuration where the first and second semiconductor chips receive power through their rear surfaces, with the first chip having a narrower width than the second, and utilizes through vias and redistribution structures to minimize congestion and optimize power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power wiring is congested on the chip surface to deliver power to stacked semiconductor chips, then power delivery capability is improved, but voltage drop increases and switching time lengthens
Solution Approach 1:
The patent transitions from planar power delivery to three-dimensional power delivery by routing power through vias that penetrate vertically through the substrate. This allows power to be delivered from the rear surface of each chip to the front surface, enabling stacked chip configuration while maintaining efficient power delivery without surface congestion
Solution Approach 2:
Instead of delivering power from the front surface outward, the patent inverts the approach by delivering power from the rear surface through the substrate to the front surface. This rear-surface power delivery method eliminates congestion on the chip surface and reduces voltage drop and switching time
2Area of stationary object
If semiconductor chips are stacked in perpendicular direction to achieve miniaturization, then occupied area is reduced, but power wiring complexity and voltage drop increase
Solution Approach 1:
The patent implements vertical stacking of semiconductor chips in the perpendicular direction, utilizing the third dimension (height) to achieve miniaturization. By combining this with through-substrate vias for power delivery, the design reduces occupied area while maintaining low voltage drop through direct vertical power paths
Solution Approach 2:
The patent divides the power delivery system into separate modular units - each semiconductor chip has its own substrate with dedicated through vias for power delivery. This segmentation allows independent optimization of each chip's power delivery path, reducing overall voltage drop in the stacked configuration
3Power
If through vias are used to penetrate substrate layers for power delivery, then power delivery efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms via holes and fills them with conductive material before completing the circuit layer formation. This preliminary action of creating through vias early in the manufacturing process simplifies subsequent steps and enables efficient power delivery through the substrate layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces voltage drop and shortens switching time while minimizing the occupied area, thereby enhancing performance and capacity without increasing package size.
Implementation Method 1
a first through via for power penetrating through the first substrate layer and electrically connecting the first circuit wiring structure and the first wiring structure with each other
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.