Stacked Semiconductor Package Layout for Shorter I/O Paths
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Solution Overview
Problem
Current package-on-package (POP) structures in semiconductor packaging face challenges with long I/O connection paths leading to increased power consumption and the need for large I/O drivers due to bonding wires connecting memory chips to system-on-chips, which also increase capacitance.
Innovation Solution
A semiconductor package structure where a first chip is connected to a carrier through bonding wires and a second chip is connected to the first chip through bumps, reducing the I/O connection path length and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If bonding wires are used to connect memory chip to system-on-chip, then electrical connection is achieved, but I/O connection path length increases leading to higher power consumption
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional stacked architecture with vertical bump connections. The second chip is stacked above the first chip, creating short vertical I/O paths through bumps instead of long lateral wire paths, thereby reducing connection length and power consumption
2Reliability
If bonding wires are used to connect memory chip to system-on-chip, then electrical connection is achieved, but large I/O driver is required increasing overall capacitance
Solution Approach 1:
The patent employs vertical stacking with bump connections to create direct electrical pathways between chips. This three-dimensional approach eliminates the need for large I/O drivers and reduces overall capacitance by providing short, direct connection paths instead of long wire bonds requiring significant drive capability
3Area of stationary object
If package-on-package structure is used for compactness, then area is reduced, but I/O connection path length increases
Solution Approach 1:
The patent resolves the area-length tradeoff by stacking chips vertically in the Z-dimension rather than placing them side-by-side in the XY-plane. This creates compact footprints while maintaining short vertical connection paths through bumps, avoiding the long lateral wire bonds that would otherwise be required
Data Source
AI summary
Provided is a semiconductor package structure including a carrier, a first chip, a second chip, a plurality of bonding wires, and a plurality of first bumps. The first chip is disposed on the carrier. The second chip is disposed on the first chip. The plurality of bonding wires is arranged to electrically connect the first chip and the carrier. The plurality of first bumps is arranged to electrically connect the second chip and the first chip. The plurality of first bumps is sandwiched between the second chip and the first chip.