Stacked Semiconductor Package With Side Support for Bonding Stability
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration, high speed, and structural reliability as they are required to be smaller, larger in capacity, and higher in performance.
Innovation Solution
A semiconductor package design featuring stacked semiconductor chips with varying horizontal widths and a side support layer to enhance structural reliability, including a first semiconductor chip with a first semiconductor substrate and through-electrodes, multiple second semiconductor chips with uniform horizontal widths, a third semiconductor chip with a different horizontal width, and a side support layer to stabilize the structure during bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase integration and capacity, then the device complexity and manufacturing difficulty increase, leading to structural instability and bonding defects
Solution Approach 1:
A support layer is introduced as an intermediary component between the first semiconductor chip and the third semiconductor chip. This support layer fills the gap created by the width difference and provides mechanical support to the narrower third chip, preventing excessive bending and ensuring stable bonding during the stacking process.
Solution Approach 2:
The support layer is selectively positioned only in the region where the width difference creates a gap, rather than uniformly across the entire structure. This localized approach provides necessary support where needed while maintaining the overall compactness and functionality of the stacked chip structure.
2Adaptability or versatility
If chips with different horizontal widths are used to optimize space and integration, then structural uniformity is compromised, causing bending and bonding defects
Solution Approach 1:
The support layer acts as a mediator that compensates for the width mismatch between chips. It fills the lateral gap created by the narrower third chip, providing a uniform bonding surface that ensures precise alignment and bonding between the first and third chips despite their width differences.
Solution Approach 2:
The support layer is prepared and positioned in advance before the final bonding process. This preliminary action ensures that the gap is already filled and the bonding surfaces are properly aligned, preventing bonding defects during the actual stacking and bonding operation.
3Reliability
If a support layer is added to stabilize the structure, then the device complexity increases, but without it, bonding defects occur
Solution Approach 1:
The support layer is selectively positioned only in the specific region where the width difference creates a gap, rather than being applied uniformly across the entire stacked structure. This localized approach provides necessary structural support where needed while minimizing the overall increase in device complexity.
Data Source
AI summary
A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate and a plurality of first through-electrodes passing through the first semiconductor substrate; a plurality of second semiconductor chips stacked on the first semiconductor chip, each of the plurality of second semiconductor chips including a second semiconductor substrate and a plurality of second through-electrodes passing through the second semiconductor substrate; a third semiconductor chip between the first semiconductor chip and one of the plurality of second semiconductor chips, the third semiconductor chip including a third semiconductor substrate and a plurality of third through-electrodes passing through the third semiconductor substrate; and a side support layer within a space between the third semiconductor chip and the first semiconductor chip, wherein a first horizontal width of the third semiconductor chip is different from first horizontal widths of the plurality of second semiconductor chips.