Stacked Semiconductor Package Thermal Paths Using TSVs and Bump Pads
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Solution Overview
Problem
As the number of semiconductor chips in a package increases to store high-capacity data, thermal resistance in semiconductor packages also increases, posing a challenge for effective heat management.
Innovation Solution
The semiconductor package design incorporates through silicon vias and bump pads with varying surface areas and solder bumps to create both signal transmission and thermal path connections, reducing thermal resistance by enhancing heat conduction through strategically placed second solder bumps with larger surface areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of semiconductor chips stacked in the package is increased to store high-capacity data, then the data storage capacity is improved, but the thermal resistance in the package is increased
Solution Approach 1:
The bump pad structure is segmented into multiple types (first bump pads, second bump pads with larger upper surface area, third bump pads) with different functions. The second bump pads are specifically designed with enlarged upper surface areas to serve as dedicated thermal path connections, separating the thermal conduction function from the signal transmission function. This segmentation allows multiple chips to be stacked while maintaining effective heat dissipation paths.
Solution Approach 2:
Different regions of the bump pad structure are assigned different qualities and functions. The upper surface area of second bump pads is locally enlarged compared to first and third bump pads, creating localized thermal conduction paths. This local quality enhancement at critical thermal path locations improves overall heat dissipation without requiring all bump pads to be uniformly large.
2Temperature
If the upper surface area of bump pads is increased to improve heat conduction, then the thermal resistance is reduced, but the device complexity is increased
Solution Approach 1:
The bump pad system is segmented into three distinct types with different surface area characteristics: first bump pads for signal transmission, second bump pads with enlarged upper surfaces for thermal conduction, and third bump pads for additional connections. This segmentation allows thermal management functions to be distributed across specific pad types rather than requiring all pads to be complex structures.
Solution Approach 2:
The second bump pads serve multiple functions: they provide electrical connection (like all bump pads) and simultaneously serve as thermal conduction paths due to their enlarged upper surface area. This multi-functionality reduces the need for separate dedicated thermal structures, thereby limiting the increase in device complexity while achieving improved heat conduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively decreases both horizontal and vertical thermal resistance, allowing for efficient heat dissipation and improved performance in high-bandwidth memory applications.
Implementation Method 1
first through silicon vias passing through the first substrate, first lower bump pads on the circuit layer on the first substrate, each of the first lower bump pads connected to a corresponding one of the first through silicon vias
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
A semiconductor package includes a first semiconductor chip including a circuit layer on a first substrate, first through silicon vias passing through the first substrate, first lower bump pads on the circuit layer, and a first upper bump pad and a second upper bump pad on a second surface of the first substrate, each of the first upper bump pad and the second upper bump pad connected to a corresponding one of the first through silicon vias. The package includes a second semiconductor chip including a circuit layer on a first surface of a second substrate, and second lower bump pads on the circuit layer on the second substrate. The package includes a first solder bump to bond the first upper bump pad and the second lower bump pad, and a plurality of second solder bumps to bond the second upper bump pad and the second lower bump pads.