Stacked Semiconductor Package TSV Landing on Bonding Pads
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Solution Overview
Problem
The formation of through silicon vias (TSVs) after insulation interlayers in semiconductor packages can lead to copper punch-through due to total thickness variation (TTV) during chemical mechanical planarization (CMP) processes, especially when landed on metal wirings.
Innovation Solution
The TSVs are formed to land directly on bonding pads in the outermost insulation layer, rather than metal wirings, using a via last scheme to prevent copper punch-through by ensuring the TSVs are connected to pads with a greater thickness than the metal wirings, thereby maintaining structural integrity during CMP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If TSV is formed after insulation interlayer using conventional via last scheme, then manufacturing process is simplified, but copper punch-through occurs due to TTV in CMP process
Solution Approach 1:
The patent applies preliminary action by forming the TSV before the insulation interlayer deposition rather than after. This reverse sequence allows the TSV to be established as a reference feature, and subsequent insulation layers are deposited over it, preventing the TTV-induced positioning errors that occur when TSV is formed after insulation layer stacking. The TSV is prepared in advance with proper positioning, and the insulation interlayer is then formed to cover the TSV structure.
2Reliability
If TSV lands on metal wiring in insulation interlayer, then via connection is achieved, but copper punch-through occurs due to TTV
Solution Approach 1:
The patent introduces an intermediary approach by having the TSV land on a bonding pad rather than directly on metal wiring within the insulation interlayer. The bonding pad serves as an intermediary target that is specifically designed to receive the TSV, providing a reliable connection point that is less susceptible to TTV-induced misalignment. This intermediary bonding pad structure ensures that even with thickness variations, the TSV maintains proper connection without causing copper punch-through.
3Manufacturing precision
If TSV penetrates through substrate and insulation interlayer to expose bonding pad, then process margin is provided, but manufacturing complexity increases
Solution Approach 1:
The patent applies inversion by reversing the conventional via last scheme sequence. Instead of forming TSV after insulation interlayer deposition, the TSV is formed before the insulation interlayer is deposited. This inverted sequence provides manufacturing precision by establishing the TSV as a reference feature that defines the positioning for subsequent insulation layer formation, thereby creating process margin while managing structural complexity through this sequence reversal.
Data Source
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AI summary
A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.