Stacked Semiconductor Package With Vertical Wiring and Heat Dissipation
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Solution Overview
Problem
The challenge of reducing the size of semiconductor packages while maintaining or enhancing their heat dissipation characteristics is a critical issue in the electronics industry, particularly as devices become smaller and lighter.
Innovation Solution
A semiconductor package design that includes a redistribution substrate, a chip stack structure with vertical wiring, a sealing member, and a heat dissipation metal member surrounding the sealing member, which facilitates efficient heat dissipation and reduces overall package size by eliminating horizontal space typically required for horizontal wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of semiconductor packages is reduced, then electronic apparatuses become smaller and lighter, but heat dissipation characteristics deteriorate
Solution Approach 1:
The patent transitions from horizontal wiring layout to vertical wiring architecture, utilizing the third dimension (height) to route signals. This dimensional change allows heat dissipation pathways to be optimized independently from the planar package footprint, enabling compact size while maintaining effective thermal management through vertical heat extraction paths.
Solution Approach 2:
The package structure is segmented into distinct functional layers: chip stack structure, sealing member, and heat dissipation member. This segmentation allows each component to be optimized independently - the chip stack for computational function, the sealing member for protection, and the heat dissipation member specifically for thermal management, resolving the contradiction between compact size and heat dissipation.
2Volume of moving object
If horizontal wiring space is eliminated to reduce package size, then compactness is improved, but heat dissipation pathways are reduced
Solution Approach 1:
The patent creates vertical heat dissipation pathways that extend through the sealing member and into the dedicated heat dissipation member above the chip stack. This vertical thermal pathway replaces traditional horizontal heat spreaders, allowing heat to escape upward through the z-dimension rather than requiring lateral space in the x-y plane.
Solution Approach 2:
The heat dissipation member serves multiple functions: it acts as a thermal sink for the chip stack, provides electromagnetic shielding, and forms part of the package structure. This multi-functionality allows a single component to address heat dissipation without requiring additional space-consuming elements.
3Area of stationary object
If vertical wiring is implemented to reduce package size, then area is reduced, but manufacturing complexity increases
Solution Approach 1:
The vertical wires are formed through the substrate before the chip stack is assembled and sealed. This preliminary formation of vertical interconnects simplifies subsequent assembly steps, as the wiring architecture is already in place to receive the chip stack, reducing overall manufacturing complexity despite the advanced vertical interconnection technology required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a compact semiconductor package with improved heat dissipation capabilities and electromagnetic interference shielding, effectively managing heat generated by stacked semiconductor chips.
Implementation Method 1
a heat dissipation metal member disposed on side surfaces and an upper surface of the sealing member
Implementation Method 2
an upper plate to which an uppermost semiconductor chip of the chip stack structure is adhered by a thermal interface adhesive layer
Data Source
AI summary
A semiconductor package includes a redistribution substrate, a chip stack structure disposed on the redistribution substrate and including a plurality of semiconductor chips disposed in a stack, a vertical wiring portion connecting the chip stack structure to the redistribution substrate and including a plurality of vertical wires that extend in a direction perpendicular to an upper surface of the redistribution substrate, a sealing member configured to seal at least a portion the chip stack structure and the vertical wiring portion, and a heat dissipation metal member disposed on side surfaces and an upper surface of the sealing member.