Stacked Semiconductor Package with Vertical Interconnects for Signal Integrity
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Solution Overview
Problem
Chip-on-chip (CoC) packages face challenges with signal integrity and high impedance due to high resistance and long transmission paths, limiting high-speed data rates in applications like silicon photonics and optical engines.
Innovation Solution
The electronic device package employs conductive structures such as conductive pillars for die-to-die and die-to-circuit layer connections, reducing transmission path length and impedance, and incorporating a redistribution trace layer for fan-out structures to enhance signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect stacked electronic components, then electrical communication between components is achieved, but high resistance and long transmission path cause signal integrity degradation and high impedance
Solution Approach 1:
The patent transitions from lateral wire bonding to vertical conductive pillar connections through redistribution layers. Conductive structures extend downward from the active surface into the substrate, creating three-dimensional electrical pathways that significantly shorten transmission distance compared to traditional wire bonding methods.
Solution Approach 2:
Redistribution trace layers serve as intermediary structures that facilitate short-distance vertical electrical connections between stacked semiconductor dies. These conductive layers act as mediators, replacing long wire bonds with localized conductive pathways through the substrate.
2Productivity
If wire bonding is used for electrical communication, then components can be connected, but high impedance prevents high speed data rate realization
Solution Approach 1:
The invention uses vertical conductive pillars extending into the substrate to create low-impedance pathways. This three-dimensional connection architecture reduces impedance by providing direct vertical electrical access rather than relying on high-impedance wire bonds.
Solution Approach 2:
The patent employs composite conductive structures combining multiple materials (copper pillars, aluminum redistribution layers, tungsten vias) to optimize electrical performance. This multi-material approach enables simultaneous achievement of low impedance and high current carrying capacity for high-speed data transmission.
3Speed
If conventional CoC package structure is used, then two electronic components can be stacked, but signal loss increases in high frequency applications
Solution Approach 1:
The patent implements vertical signal pathways through conductive pillars that extend downward from the active surface. This vertical routing reduces signal path length and minimizes exposure to lossy lateral interconnect structures, thereby reducing signal attenuation in high-frequency applications.
Solution Approach 2:
The invention replaces mechanical wire bonding with direct physical contact through conductive pillars embedded in the substrate. This substitution eliminates the mechanical wire bond interface that causes signal loss, achieving better high-frequency performance through direct metallurgical or physical contact.
Data Source
AI summary
An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.