Stacked Semiconductor Package Structure to Minimize Warpage
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Solution Overview
Problem
The semiconductor industry faces challenges in creating smaller and more efficient packaging techniques for semiconductor dies, particularly in stacking multiple dies to achieve high integration and component density, while minimizing material delamination and warpage during the manufacturing process.
Innovation Solution
A method involving a face-to-back die stacking configuration with hybrid bonding and a combination of patterning and sawing processes to form semiconductor devices, followed by encapsulation and redistribution structures, which enhances bonding strength and reduces material delamination and warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor dies are stacked to achieve high integration density, then component density and integration level are improved, but material delamination and warpage occur during manufacturing
Solution Approach 1:
The patent applies preliminary action by forming a compliance layer and stress compensation structures before stacking the semiconductor dies. These structures are pre-configured to counteract the thermal expansion differences and mechanical stresses that will occur during subsequent packaging and operation, thereby preventing delamination and warpage before they can occur
Solution Approach 2:
The patent uses composite materials by combining semiconductor dies with different material properties (e.g., different thermal expansion coefficients) in a stacked configuration, and introducing intermediate compliance layers made of materials that bridge the mechanical properties between rigid dies and flexible packaging, creating a composite structure that manages stress and prevents delamination
2Quantity of substance
If multiple semiconductor dies are stacked to achieve high integration density, then component density and integration level are improved, but material warpage occurs during manufacturing
Solution Approach 1:
The patent applies parameter changes by modifying the mechanical and thermal parameters of the stacked structure through the compliance layer and stress compensation structures. These structures change the effective thermal expansion coefficient and mechanical compliance of the overall assembly, allowing the package to accommodate dimensional changes without warping during temperature cycling and manufacturing processes
3Strength
If face-to-back die stacking with hybrid bonding is used, then bonding strength is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the bonding interface into two distinct configurations: face-to-face bonding for electrical interconnection and back-to-back bonding for mechanical support and alignment. This segmentation allows each bonding interface to be optimized for its specific function, simplifying the overall manufacturing process while achieving high bonding strength through hybrid bonding
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a plurality of semiconductor dies, a dielectric layer, a connector, and a passivation layer. The plurality of semiconductor dies are stacked on one another and disposed over the semiconductor substrate. The dielectric layer cover a top surface and a side surface of the each of the plurality of semiconductor dies. The connector is disposed over a topmost one of the plurality of semiconductor dies. The passivation layer is disposed over the dielectric layer and laterally surrounds the connector, wherein, from a cross sectional view, an acute angle is included between an outermost side surface of the passivation layer and a bottom surface of the passivation layer.