Stacked Semiconductor Package Structure for Warpage and Delamination

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving miniaturization, weight reduction, high performance, high capacity, and high reliability, particularly in stacked semiconductor chip structures.

Innovation Solution

The semiconductor package design includes a base chip with a passivation layer, a semiconductor chip with a bump and underfill layer, an encapsulant, and an organic material layer, where the base chip is made of silicon, and the organic material layer is made of photosensitive polyimide, enhancing adhesion and reducing warpage and delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If semiconductor chips are stacked in multiple stages to achieve miniaturization and high capacity, then the density and capacity of the semiconductor package are improved, but the reliability and production yield deteriorate due to increased complexity and potential adhesion issues

Engineering Contradiction:
Improvechip stacking capacityVSAvoidpackage reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by selectively forming an organic material layer only in specific regions (second region) of the passivation layer, rather than uniformly across the entire surface. This localized approach addresses adhesion concerns at critical interfaces while maintaining the miniaturized stacked structure, thereby improving reliability without sacrificing chip stacking capacity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The organic material layer acts as an intermediary between the passivation layer and the underfill layer or encapsulant. This intermediate layer improves interfacial adhesion and reduces warpage in the stacked semiconductor package, resolving the reliability issues that arise from multi-stage stacking while maintaining high capacity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of moving object

If the base chip area is reduced to achieve miniaturization, then the size and weight of the semiconductor package are reduced, but the adhesion between layers deteriorates leading to warpage and reliability issues

Engineering Contradiction:
Improvebase chip areaVSAvoidlayer adhesion
Core Design Contradiction:
Area of moving objectVSStrength

Solution Approach 1:

The patent forms an organic material layer in a specific second region of the passivation layer, creating local quality enhancement at the interface where adhesion is most critical. This allows miniaturization of the base chip area while maintaining strong layer adhesion through the strategically placed organic material layer, preventing warpage and improving reliability

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the material parameter by introducing an organic material layer with different physical and chemical properties than the inorganic passivation layer. This parameter change improves adhesion strength and reduces warpage in the miniaturized package structure, resolving the contradiction between reduced area and maintained strength

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves the reliability and production yield of semiconductor packages by stabilizing the semiconductor chip structure under varying temperatures and preventing delamination.

Implementation Method 1

an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS12604751B2Semiconductor package
Publication Date: 2026.04.14 SAMSUNG ELECTRONICS CO LTD
  • US12604751B2 patent drawing
  • US12604751B2 patent drawing
  • US12604751B2 patent drawing

AI summary

A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.