Stacked Semiconductor Package Layout for Shorter Wire Paths
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Solution Overview
Problem
Existing semiconductor packages face challenges in miniaturization and spatial constraints, leading to increased connection distances of wires for signal connection and reduced reliability of semiconductor chips due to spatial limitations.
Innovation Solution
The semiconductor package design includes asymmetrical molding members with varying widths and heights to reduce connection distances between semiconductor chips while enhancing protection and reliability, utilizing an encapsulation to cover the periphery of these chips and molding members.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of semiconductor chips is increased to achieve high performance and high capacity, then the functional capacity is improved, but the spatial constraint and connection distance are worsened
Solution Approach 1:
The patent transitions from a conventional two-dimensional chip arrangement to a three-dimensional stacked configuration. Multiple semiconductor chips are vertically stacked and interconnected through through-silicon vias (TSVs), enabling signal transmission in the vertical dimension. This dimensional change allows more chips to be packed into a smaller footprint area while maintaining short connection distances through vertical interconnects rather than horizontal wire traces.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are stacked vertically with each chip containing functional circuits and interconnect structures. The chips are nested in multiple layers with TSVs providing vertical pathways through each chip layer, creating a compact nested arrangement that maximizes chip density while minimizing overall package size and connection distances.
2Area of stationary object
If semiconductor chips are densely arranged to reduce package size, then miniaturization is achieved, but the reliability of chip mounting is worsened due to spatial constraints
Solution Approach 1:
The patent employs asymmetric molding members with different widths in different regions. The molding members have a first width in a first region and a second width in a second region, creating an asymmetric structure that provides enhanced protection in critical areas while optimizing space utilization. This asymmetric design allows for improved chip reliability through targeted protection without increasing overall package size.
Solution Approach 2:
The patent implements local quality variations through the asymmetric molding members that provide different levels of protection in different regions. The molding members have varying widths to provide enhanced mechanical support and protection in regions where chips are mounted, while maintaining compact dimensions in other regions. This localized quality optimization ensures chip reliability in critical mounting areas without compromising miniaturization goals.
3Speed
If asymmetrical molding members with varying widths are used to reduce connection distance, then signal transmission efficiency is improved, but the device complexity is worsened
Solution Approach 1:
The patent utilizes asymmetric molding members with different widths in different regions to optimize the package layout and reduce connection distances between chips. The asymmetric structure allows for compact chip arrangement and shorter signal paths, improving transmission efficiency. Despite the asymmetric geometry, the molding members are formed as single continuous structures that can be manufactured using standard molding processes, thereby limiting the increase in device complexity.
Data Source
AI summary
Provided is a semiconductor package including a package substrate, a pair of first semiconductor chips on the package substrate and facing each other in a horizontal direction, a pair of second semiconductor chips on the pair of first semiconductor chips and facing each other in the horizontal direction, and a pair of molding members covering a periphery of the pair of second semiconductor chips on the pair of first semiconductor chip and a part of the pair of molding members on the package substrate, each of the pair of molding members include first and second widths in the horizontal direction, the first width in a first region where the pair of second semiconductor chips face each other is less than the second width in a second region where the pair of second semiconductor chips do not face each other.