Stacked Semiconductor Package Without TSV Interposer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high manufacturing cost and increased interconnection length due to the use of Through Silicon Via (TSV) technology in interposers lead to higher resistance and reduced performance in semiconductor devices.
Innovation Solution
A semiconductor package structure that eliminates the interposer by using a lower and upper redistribution wiring layer with conductive connectors and conductive bumps to electrically connect logic and memory semiconductor chips, reducing the interconnection distance and manufacturing cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interposer manufactured using Through Silicon Via (TSV) technology is used to connect semiconductor chips, then electrical connection between chips is achieved, but manufacturing cost increases and interconnection length increases leading to higher resistance and reduced performance
Solution Approach 1:
The patent extracts and removes the interposer component from the system by implementing direct chip-to-chip bonding. The lower redistribution wiring layer is directly bonded to the logic semiconductor chip without requiring an intermediate interposer substrate, thereby eliminating TSV manufacturing processes and associated costs while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from a planar interposer-based connection architecture to a vertical stacked architecture where the lower redistribution wiring layer is directly bonded to the logic chip. This dimensional reorganization eliminates the horizontal interposer layer and creates direct vertical electrical pathways, reducing both cost and interconnection length.
2Reliability
If an interposer with conductive wirings is used to connect semiconductor chips, then electrical connection is established, but interconnection length increases causing increased resistance and reduced device performance
Solution Approach 1:
The patent removes the interposer and its conductive wirings from the system, replacing them with direct bonding between the lower redistribution wiring layer and the logic semiconductor chip. This extraction eliminates the intermediate connection path that contributed to increased resistance and improved device performance.
3Adaptability or versatility
If a conventional SiP structure with interposer is used, then multiple semiconductor chips can be mounted, but package size and manufacturing cost increase
Solution Approach 1:
The patent implements a three-dimensional stacked architecture where multiple semiconductor chips are mounted vertically one above the other with direct bonding. This vertical stacking in the Z-dimension eliminates the need for a large horizontal interposer substrate, thereby reducing package footprint area while maintaining multi-chip mounting capability.
Solution Approach 2:
The patent creates a nested vertical structure where the upper redistribution wiring layer is positioned directly above the lower redistribution wiring layer, with conductive connectors extending through the sealing member to establish electrical connections between stacked chips. This nested arrangement maximizes space utilization and reduces overall package size.
Data Source
AI summary
A semiconductor package includes: a lower redistribution wiring layer having: a first chip mounting region; a peripheral region, and lower redistribution wirings; a logic semiconductor chip mounted in the first chip mounting region, the logic semiconductor chip having a plurality of first through electrodes that are electrically connected to at least some of the lower redistribution wirings; a first sealing member covering the logic semiconductor chip, a plurality of conductive connectors penetrating the first sealing member in the peripheral region; an upper redistribution wiring layer provided on the first seal and having upper redistribution wirings that are electrically connected to the plurality of conductive connectors, the upper redistribution wiring layer having at least one second chip mounting region that overlaps at least a portion of the first chip mounting region; and at least one memory semiconductor chip mounted in the second chip mounting region using first and second conductive bumps.