Stacked Semiconductor Pad Structure for Dishing-Resistant Bonding
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Solution Overview
Problem
Existing semiconductor packages face challenges in integrating multiple chips with high capacitance, thinness, and miniaturization while maintaining excellent bonding interfaces and electrical properties.
Innovation Solution
A semiconductor package design featuring a stack of semiconductor chips with large-area pads that include insulating pattern layers to control dishing and erosion, and a manufacturing method that forms pads with alternating conductive and insulating layers to enhance bonding quality and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large-area pads are used to improve electrical properties and power integrity, then electrical conductivity and power delivery are enhanced, but dishing and erosion occur during bonding processes
Solution Approach 1:
The pad structure is divided into multiple layers with different materials and properties. The base layer provides large area for electrical conductivity, while the patterned insulating layer (with openings) provides localized protection against dishing and erosion. This local differentiation of properties allows simultaneous achievement of electrical performance and bonding quality.
Solution Approach 2:
The pad structure uses composite materials including conductive materials (copper, aluminum, tungsten) for electrical connectivity and insulating materials (silicon oxide, silicon nitride, silicon oxynitride) for protection. This composite structure enables both large-area electrical properties and resistance to bonding defects.
2Productivity
If multiple semiconductor chips are integrated into a stack to achieve miniaturization and high capacitance, then component density and functionality are improved, but bonding interface quality and electrical connectivity become more difficult to maintain
Solution Approach 1:
Each chip in the stack is segmented into functional regions including pads with patterned insulating layers. This segmentation allows for optimized bonding interfaces at each chip level, ensuring quality connectivity while maintaining high integration density across the multi-chip stack.
Solution Approach 2:
The patterned insulating layer is formed on the pads before the bonding process. This preliminary action protects the pad surfaces from dishing and erosion that would otherwise occur during bonding, ensuring high-quality bonding interfaces are achieved even in multi-chip stacks.
3Length of moving object
If pads are made thinner to achieve overall chip thinness, then chip profile and miniaturization are improved, but electrical conductivity and bonding reliability deteriorate
Solution Approach 1:
The pad uses composite material structure with a thick base layer (5 μm to 20 μm) providing electrical conductivity and a patterned insulating layer for protection. This composite approach maintains electrical performance while allowing overall chip thinness through optimized layer configuration.
Solution Approach 2:
The insulating patterned layer is applied locally on the pad surface rather than uniformly throughout the pad thickness. This local quality approach preserves electrical conductivity through the pad thickness while providing surface protection, enabling thin chip design without sacrificing electrical performance.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads on the first substrate, and a plurality of through-electrodes extending through the first substrate and connected to the plurality of first pads, and a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second substrate, and a plurality of second pads below the second substrate and in contact with the plurality of first pads. The plurality of first pads includes a first group of first pads each including a first base layer including a first recess, and a first conductive pattern layer and a first insulating pattern layer alternately disposed in the first recess, and a second group of first pads each including a second base layer including a second recess, and a second conductive pattern layer disposed in the second recess.