Stacked PCB Capacitor Module for Low Inductance Power Delivery

The patent transitions from planar capacitor placement to three-dimensional vertical stacking of PCBs. Multiple PCBs are stacked with capacitors positioned between them, utilizing the vertical dimension to achieve high capacitance without consuming additional board space. The electrical contacts extend through multiple layers to connect capacitors across stacked PCBs, enabling compact high-capacitance configuration.

The patent implements localized capacitor placement in close proximity to power consumption sites on each PCB layer. By positioning capacitors immediately adjacent to high-current transient sources and using short vertical connection paths through electrical contacts, the design minimizes loop area and thus reduces parasitic inductance and resistance while maintaining effective capacitance where it is most needed.

The patent implements a modular stacked PCB architecture where individual PCBs with capacitors can be dynamically added or removed from the stack based on varying power requirements. This dynamic configuration allows the system to adjust total capacitance levels flexibly while maintaining voltage stability, enabling adaptation to different power consumption scenarios without redesigning the entire system.