Stacked Pixel Counter Layout for High-Density Image Sensors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing solid-state imaging devices face challenges in achieving high resolution and power efficiency due to the large area required by counter circuits, which limits pixel density and frame rate, and increases power consumption in shared wiring.
Innovation Solution
A solid-state imaging device is designed with a stacked structure, featuring a photoelectric converter and a counter with separate bit group counters in different layers, connected by an integrated circuit, to reduce the number of through electrodes and optimize signal processing, allowing for higher integration and efficient power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If counter circuits are arranged in a flat array for each pixel to achieve high resolution, then pixel density is improved, but the area required by counter circuits increases
Solution Approach 1:
The patent transitions from a two-dimensional flat array arrangement to a three-dimensional stacked architecture. Counter circuits are distributed across multiple layers (first layer, second layer, third layer), with through-electrodes connecting corresponding pixels vertically. This vertical stacking enables high pixel density while confining counter circuit area to specific layers, resolving the area-contradiction.
Solution Approach 2:
The counter circuit functionality is segmented across multiple layers. Each layer contains a portion of the counter circuits (e.g., first layer has counters for first bit group, second layer has counters for second bit group). This segmentation allows parallel processing and reduces the area required in any single layer while maintaining total counting capacity.
2Measurement precision
If the number of pixels is increased to achieve high resolution, then pixel density is improved, but switching speed must be increased to maintain frame rate
Solution Approach 1:
The pixel array is segmented into multiple independent layers, each with its own counter circuits. Multiple pixels can be processed in parallel across different layers simultaneously, effectively increasing the overall switching capacity without requiring faster switching within each individual pixel circuit.
Solution Approach 2:
By adding the vertical dimension with multiple layers, the system achieves parallel processing capability. Through-electrodes enable simultaneous signal transmission across layers, increasing effective switching speed while maintaining high pixel density through the stacked architecture.
3Device complexity
If common signal lines and output pads are used to reduce through electrodes, then device complexity is reduced, but power consumption in shared wiring increases
Solution Approach 1:
The patent utilizes the vertical dimension with through-electrodes to create dedicated vertical signal paths. Instead of horizontal sharing that causes power consumption issues, each layer has direct vertical connections to output pads, reducing current load on shared horizontal wiring while maintaining low device complexity through the stacked design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances pixel density, maintains high resolution, and reduces power consumption by optimizing signal processing and interlayer connections, enabling more efficient image capture.
Implementation Method 1
A solid-state imaging device receives light incident from a subject, converts the received light into photoelectricity, and generates an electrical signal
Data Source
AI summary
A solid-state imaging device with increased integration is provided. A pixel of the solid-state imaging device includes a photoelectric converter and a counter that counts a pulse signal output based on the amount of light incident on the photoelectric converter, wherein the counter may be divided into a lower bit group and an upper bit group, a first integrated circuit is provided between the lower bit group and the upper bit group, and the first integrated circuit may connect the lower bit group and the upper bit group of a plurality of pixels to each other.