Stacked Pixel Architecture for Flexible Solid-State Imaging Readout
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Solution Overview
Problem
Current solid-state imaging devices lack flexibility in design, particularly in the integration of photoelectric converters and pixel transistors, which limits their performance and adaptability.
Innovation Solution
A solid-state imaging device with a stacked structure of semiconductor layers, where a first semiconductor layer includes a photoelectric converter and an electric charge accumulation section, and a second semiconductor layer with a pixel transistor is stacked on the first layer, featuring a pixel separation section, insulating regions, and through electrodes for electrical coupling, allowing for more flexible design and improved signal readout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If photoelectric converter and pixel transistor are integrated in the same semiconductor layer, then device complexity is reduced, but design flexibility and signal readout efficiency deteriorate
Solution Approach 1:
The device is divided into two separate semiconductor layers: a first semiconductor layer containing the photoelectric converter and charge accumulation section, and a second semiconductor layer containing the pixel transistor. This segmentation allows independent optimization of each layer's design and function, resolving the contradiction between integration simplicity and design flexibility.
Solution Approach 2:
The photoelectric converter and pixel transistor are separated in the vertical dimension (different semiconductor layers) rather than being integrated in the same horizontal plane. This dimensional separation enables independent design optimization while maintaining functional connectivity through vertical coupling structures.
2Ease of manufacture
If photoelectric converter and pixel transistor are integrated in the same semiconductor layer, then manufacturing process is simplified, but signal readout efficiency deteriorates
Solution Approach 1:
By segmenting the device into separate semiconductor layers for photoelectric conversion and signal processing, the patent enables optimized signal readout paths through dedicated coupling structures (through electrodes and coupling sections) that improve readout efficiency while maintaining manufacturability through standardized layering processes.
3Adaptability or versatility
If stacked structure with separate semiconductor layers is used, then design flexibility and signal readout efficiency are improved, but device complexity increases
Solution Approach 1:
The patent uses vertical stacking of semiconductor layers to achieve design flexibility without significantly increasing horizontal device complexity. The multi-layer structure organizes different functional components in the vertical dimension, allowing independent design optimization while maintaining a compact overall footprint.
Solution Approach 2:
Through electrodes and coupling sections act as intermediary structures that connect the first and second semiconductor layers. These intermediaries simplify the interface between layers, making the stacked structure more manageable and less complex than direct integration would require.
4Productivity
If stacked structure with separate semiconductor layers is used, then signal readout efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The through electrodes and coupling sections serve as intermediary structures that facilitate signal transfer between layers. These standardized intermediary components simplify the manufacturing process by providing repeatable, modular connection methods that reduce the complexity of assembling multi-layer structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the flexibility and efficiency of signal readout in solid-state imaging devices, enabling better performance and adaptability in imaging applications.
Implementation Method 1
a through electrode that penetrates through the insulating region in a thickness direction and is electrically coupled to the first semiconductor layer
Implementation Method 2
a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated
Data Source
AI summary
There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.