Stacked Planar Terminals for Low Inductance Semiconductor Devices
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Solution Overview
Problem
Traditional semiconductor devices have high inductance due to the area between busbars and bond wire loops, which affects their efficiency in conducting and converting current, particularly in applications like power inverters, where reduced inductance is desirable without compromising current conduction.
Innovation Solution
The implementation of stacked planar terminals that abut and overlap silicon dies, reducing the area between busbars and bond wire loops, and integrating busbar structures within the housing to minimize inductance and enhance thermal and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional lead configurations are used, then the device structure is simple, but the inductance is high which reduces efficiency
Solution Approach 1:
The patent transitions from planar lead arrangements to three-dimensional stacked terminal structures. Multiple terminals are arranged vertically in layers, with lower terminals extending from the housing bottom and upper terminals extending from the housing top, creating a stacked configuration that reduces current loop area and inductance while maintaining structural manageability.
Solution Approach 2:
The patent implements a nested terminal structure where upper terminals are positioned above and connected to lower terminals through vertical interconnections within the housing. The terminals are arranged in concentric or nested patterns, with inner terminals surrounded by outer terminals, creating compact current paths that minimize inductance.
2Productivity
If stacked planar terminals are implemented, then inductance is reduced and efficiency improved, but manufacturing and assembly complexity increases
Solution Approach 1:
The terminal structure is divided into discrete modular units with standardized connection interfaces. Each terminal layer can be independently manufactured and then assembled together, allowing for modular production that simplifies the manufacturing process while achieving the low-inductance stacked configuration.
Solution Approach 2:
The patent designs terminals with universal connection features that can accommodate different semiconductor device configurations. The standardized terminal structures and connection methods can be applied across various device types and power ratings, reducing the need for custom manufacturing processes.
Data Source
AI summary
A semiconductor device includes housing, a substrate, a first semiconductor die, a second semiconductor die, a first terminal, and a second terminal. The first terminal in a first terminal plane couples to the first semiconductor die. The second terminal has a contact portion in a contact portion plane within the housing that couples to the second semiconductor die, a main portion in a main portion plane partially within the housing, the main portion plane substantially parallel to and offset from the first terminal plane, and the main portion plane substantially parallel to and offset from the contact portion plane, and an offsetting portion within the housing and that connects the contact portion to the main portion. At least some of the main portion of the second terminal overlaps the first terminal and the first terminal and the main portion of the second terminal extend from the housing in a same direction.