Stacked Plate Capacitor Layout for Leakage and Breakdown Balance

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving low current leakage and good time-dependent dielectric breakdown (TDDB) and breakdown voltage (VBD) simultaneously due to issues at the corners of conductive plates in plate capacitors.

Innovation Solution

A plate capacitor structure with multiple conductive plates stacked in sequence, featuring alternating large and small plates, where the sizes progressively decrease towards the top, and some corners are covered while others are exposed, ensuring balanced performance by controlling distances between adjacent plates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If all corners of conductive plates are covered by adjacent plates, then current leakage is reduced, but TDDB and VBD performance deteriorate due to stress concentration

Engineering Contradiction:
Improvecurrent leakageVSAvoidTDDB and VBD performance
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent applies local quality by differentiating the treatment of corners: some corners are covered by adjacent plates while others are exposed. Specifically, first corners of the first conductive plate are covered by the second conductive plate, while second corners are exposed. This localized differentiation allows the structure to reduce current leakage at covered corners while maintaining TDDB and VBD performance at exposed corners, resolving the contradiction between these two performance metrics.

Inventive Principle:
Principle #3Local quality

2Productivity

If capacitor size is reduced for higher device density, then device density improves, but current leakage and breakdown voltage issues worsen

Engineering Contradiction:
Improvedevice densityVSAvoidcurrent leakage
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the capacitor structure into multiple conductive plates (first, second, third, and fourth conductive plates) with alternating sizes and configurations. This segmentation allows each plate to be optimized independently for density while the collective structure maintains low current leakage through the selective corner coverage pattern, resolving the contradiction between device density and current leakage.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If capacitor structure is simplified, then manufacturing ease improves, but performance optimization deteriorates

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidcapacitor performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent employs asymmetry in the capacitor structure with alternating large and small conductive plates, where each plate has different dimensions and corner configurations. The first and third conductive plates have different sizes, and the second and fourth conductive plates have different sizes, creating an asymmetric pattern that optimizes performance while maintaining manufacturability through systematic variation rather than complex arbitrary designs.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20250316422A1Capacitor structure, semiconductor structure, and method for manufacturing the same
Publication Date: 2025.10.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250316422A1 patent drawing
  • US20250316422A1 patent drawing
  • US20250316422A1 patent drawing

AI summary

A method for manufacturing a semiconductor structure is provided. A first plate, a second plate, and a third plate are sequentially formed over a substrate. The first plate includes a first top surface, first sidewalls and first transition regions, wherein the first transition regions connect the first sidewalls to the first top surface. The second plate includes a second top surface, second sidewalls and second transition regions, wherein the second transition regions connect the second sidewalls to the second top surface, and the first transition regions are exposed by the second plate. The third plate includes a third top surface, third sidewalls and third transition regions, wherein the third transition regions connect the third sidewalls to the third top surface, and the second transition regions are covered by the third plate.