Power electronics assembly having staggered and diagonally arranged transistors
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Solution Overview
Problem
Existing power electronics assemblies face challenges in reducing size and minimizing parasitic inductance and thermal effects due to the relative placement of power electronic devices, gate drive devices, and capacitors, which impact performance and size.
Innovation Solution
The power electronics assembly features diagonally offset transistors in multiple modules, with staggered arrangements and hybrid cooling structures that include two-phase and single-phase cooling portions to efficiently distribute heat and reduce size, while minimizing parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power electronic devices are placed separately from gate drive devices and capacitors, then electrical performance is improved by reducing parasitic inductance, but device complexity and size increase
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration, placing power electronic devices, gate drive devices, and capacitors in different vertical layers. This dimensional change allows all components to be integrated in a compact footprint while maintaining the electrical performance benefits of separate component placement by minimizing parasitic inductance through optimized vertical interconnections.
2Reliability
If power electronic devices are placed separately from gate drive devices and capacitors, then parasitic inductance is reduced, but overall assembly size increases
Solution Approach 1:
The patent implements a nested configuration where gate drive devices and capacitors are positioned within the vertical projection area of power electronic devices, and multiple functional layers are stacked within each other's spatial envelope. This nesting approach reduces the overall assembly footprint while maintaining the electrical isolation needed to minimize parasitic inductance between components.
3Volume of moving object
If transistors are arranged in a compact configuration, then assembly size is reduced, but heat concentration increases
Solution Approach 1:
The patent segments the power electronic devices into multiple discrete transistor modules arranged in a staggered diagonal pattern across different vertical layers. This segmentation distributes heat generation across multiple spatial zones and thermal pathways, preventing heat concentration in a single location while maintaining compact overall dimensions through the integrated stacked architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances thermal and electrical performance by reducing heat concentration and parasitic inductance, allowing for a smaller overall size of the power electronics assembly.
Implementation Method 1
the first and second hybrid cooling assemblies each include a first cooling portion that aligns with and cools one or more of the first and second transistors, respectively, and a second cooling portion that does not align with any transistor
Implementation Method 2
the first and second hybrid cooling assemblies each include a first cooling portion that aligns with and cools one or more of the first and second transistors, respectively
Data Source
AI summary
Methods, apparatuses and systems to provide for technology to that includes a first power electronics module including a plurality of first transistors that are diagonally offset from each other, and a second power electronics module stacked on the first power electronics module. The second power electronics module includes second transistors that are diagonally offset from each other. The second transistors are staggered relative to the first transistors.