Stacked Power Structure for Low-Parasitic High-Frequency Packaging
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Solution Overview
Problem
Current power supply products fail to achieve the required integration degree for high-frequency and high-power applications, with large parasitic parameters hindering their performance and adaptability to miniaturization trends.
Innovation Solution
A power structure comprising a dual-substrate configuration with a power chip on one substrate and a driver chip on the other, connected by a conductive part that electrically interconnects them, reducing parasitic parameters and enhancing integration and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a current power supply product structure is used, then the product can be manufactured with existing technology, but the integration degree is insufficient and parasitic parameters are large, failing to meet high-frequency and high-power requirements
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked configuration, placing the driver chip and power chip on different substrates (first substrate and second substrate) stacked vertically. This dimensional change enables higher integration density while reducing parasitic parameters through shorter current paths and improved electrical connectivity between chips.
Solution Approach 2:
The patent implements a nested packaging structure where the driver chip is mounted on the first substrate, which is then packaged together with the power chip on the second substrate. The conductive parts penetrate through the package body to establish electrical connections, creating a compact nested arrangement that reduces overall device size and parasitic inductance.
2Volume of moving object
If the power supply product is miniaturized to meet outline dimension requirements, then the product size is reduced, but the integration degree and performance for high-frequency applications are compromised
Solution Approach 1:
By stacking substrates vertically rather than expanding horizontally, the patent achieves miniaturization in the planar dimensions while maintaining or improving integration degree through the third dimension. The vertical stacking allows multiple functional chips to be integrated in a compact footprint.
Solution Approach 2:
The patent divides the power supply function into separate driver chip and power chip modules mounted on different substrates. This segmentation allows each chip to be optimized independently while the stacked configuration maintains compact overall dimensions, resolving the conflict between miniaturization and integration.
3Power
If high power and high frequency requirements are met, then performance is improved, but parasitic parameters become too large for the current product structure
Solution Approach 1:
The vertical stacking configuration creates shorter and more direct current paths between the driver chip and power chip compared to planar layouts. This reduces parasitic inductance and resistance, enabling the structure to handle high-power and high-frequency operations effectively.
Solution Approach 2:
The conductive parts serving as tabs act as intermediaries that provide low-inductance electrical connections between the driver chip, power chip, and external circuitry. These conductive structures are specifically designed to minimize parasitic parameters while facilitating high-frequency signal and power transmission.
Data Source
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AI summary
Embodiments of this application disclose a power structure, a preparation method, and a device, to provide a power structure with a high integration degree, to meet a requirement of the high-frequency and high-power field. The embodiments of this application provide a power structure, including a first substrate, a second substrate, a driver chip, a power chip, and a conductive part. A first surface of the first substrate and a second surface of the second substrate are disposed opposite to each other; a first end of the conductive part is connected to the first surface, and a second end of the conductive part is connected to the second surface; the driver chip is disposed on the first substrate; and the power chip is disposed on the second substrate.