Stacked RC Filter Layout for Compact ASK Demodulation Circuits
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Solution Overview
Problem
There is a demand for reducing the layout area of semiconductor devices that include filter circuits, particularly in contactless IC cards, to accommodate increased communication rates and maintain signal integrity while minimizing the impact of DC offset and temperature drift.
Innovation Solution
The semiconductor device incorporates a filter circuit with a resistor, MOS capacitor, and MOM capacitor stacked in specific configurations to optimize layout area efficiency, using guard rings to inhibit external influences and variations, and includes a high-pass filter, amplifier circuit, comparator with adjustable hysteresis, and trimming circuit to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the layout area of the filter circuit is reduced, then the space efficiency is improved, but the signal integrity and filter performance deteriorate
Solution Approach 1:
The patent transitions from planar layout to three-dimensional stacked configuration, placing capacitors vertically above resistors. This dimensional change allows the filter circuit to maintain adequate component areas for signal integrity while reducing the overall footprint area, directly resolving the contradiction between compact layout and maintained signal quality
Solution Approach 2:
The patent implements nesting by positioning capacitor structures within the vertical space above resistor elements. The capacitor electrodes are arranged to overlap with resistor regions in the plan view, effectively nesting multiple components in the same footprint area while maintaining their electrical functions and signal integrity
2Speed
If the communication rate is increased, then the data transmission speed is improved, but the DC offset and temperature drift effects worsen
Solution Approach 1:
The patent segments the filter circuit into multiple independent stacked modules, each consisting of a resistor and capacitor pair. This segmentation allows for better control and compensation of DC offset and temperature drift effects, as each module can be independently optimized and their effects averaged or compensated, enabling higher communication rates with reduced harmful factors
Solution Approach 2:
The patent implements a feedback mechanism through the stacked RC filter configuration, where the capacitive elements provide frequency-selective feedback that compensates for DC offset and temperature-induced drift. The filter's frequency response characteristics, achieved through the stacked configuration, actively counteract these harmful effects, allowing increased communication rates
Data Source
AI summary
A semiconductor device includes: a filter circuit including: a resistor; a MOS capacitor; and a MOM capacitor stacked on at least one of the resistor or the MOS capacitor, wherein the following inequalities are satisfied:Mc≥β−γ/β+γ×Mr Mr≤√{square root over (1/2πftαβ)} [Math. 1]where ft denotes a cutoff frequency of the filter circuit, Mr denotes a resistor area of a resistor-provided region in which the resistor is provided, Mc denotes a MOS capacitor area of a MOS capacitor-provided region in which the MOS capacitor is provided, α denotes a resistivity of the resistor, β denotes a MOS capacitance rate of the MOS capacitor, and γ denotes a MOM capacitance rate of the MOM capacitor.