Stacked ReRAM With Integrated Access Transistor
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Solution Overview
Problem
Conventional three-dimensionally stacked ReRAM structures lack the capability to include connections between a selector device and each individual ReRAM cell, with one selector device typically representing an entire wordline of cells, limiting their functionality.
Innovation Solution
A stacked ReRAM structure is developed with a dedicated selection transistor integrated into each memory cell, featuring ReRAM cell, drain, gate, and source layers insulated from each other and connected via separate contact vias, allowing individual connections between a selector device and each ReRAM cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If one selector device serves an entire wordline of cells, then device complexity is reduced, but individual cell control capability is lost
Solution Approach 1:
The patent divides the wordline into multiple segmented bitlines (first bitline and second bitline), allowing each ReRAM cell to be independently accessed through specific bitline combinations. This segmentation enables individual cell control while maintaining manageable device complexity through systematic organization.
Solution Approach 2:
The patent introduces a third dimension by stacking multiple ReRAM cells vertically at each bitline intersection point. This 3D configuration allows multiple cells to be addressed independently through the same bitlines by selecting specific cell layers, thereby providing individual cell control without increasing planar device complexity.
2Adaptability or versatility
If separate contact vias are used for each layer, then individual cell access is enabled, but manufacturing complexity increases
Solution Approach 1:
The contact via structure is segmented into multiple distinct vias (first contact via, second contact via, third contact via, fourth contact via), each providing exclusive access to specific layers. This segmentation enables precise individual cell access while the systematic arrangement facilitates standardized manufacturing processes.
Solution Approach 2:
The patent introduces intermediate contact vias that connect different ReRAM cell layers to the bitlines and wordlines. These intermediary structures mediate between the vertical stacking and the horizontal wiring, enabling individual cell access through a systematic via arrangement that can be manufactured using standard semiconductor fabrication techniques.
3Quantity of substance
If ReRAM cells are stacked in three dimensions, then memory density is increased, but connection complexity between selector devices and individual cells increases
Solution Approach 1:
The patent implements vertical stacking of multiple ReRAM cells in the third dimension, with each cell layer accessible through combinations of bitlines and wordlines. This 3D configuration increases memory density while the systematic addressing scheme (selecting specific bitline and wordline intersections) keeps connection complexity manageable through spatial organization.
Solution Approach 2:
The bitlines and wordlines serve multiple functions: they simultaneously address multiple ReRAM cells across different layers and enable individual cell selection through specific combinations. This multi-functionality reduces the need for dedicated connections to each cell, thereby increasing density without proportionally increasing connection complexity.
Data Source
AI summary
A stacked resistive random access memory (ReRAM) structure is provided. The stacked ReRAM structure includes a channel, a ReRAM cell sub-structure and a contact via sub-structure. The ReRAM cell structure includes ReRAM cell, drain, gate and source layers, which are insulated from one another and respectively disposed in operative contact with the channel. The contact via sub-structures includes first, second, third and fourth contact vias, which are separate from one another. The first contact via is disposed in exclusive operative contact with the ReRAM cell layer. The second contact via is disposed in exclusive operative contact with the drain layer. The third contact via is disposed in exclusive operative contact with the gate layer. The fourth contact via is disposed in exclusive operative contact with the source layer.