Stacked Vertical ReRAM Transistors With Shared Drain Architecture
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Solution Overview
Problem
Current semiconductor technologies face challenges in integrating high-density non-volatile memory with efficient vertical transport field effect transistors (VTFETs) and resistive random access memory (ReRAM) structures, particularly in enhancing current conductivity and reducing electroforming randomness.
Innovation Solution
A semiconductor structure comprising stacked vertical field effect transistors with a resistive random access memory (ReRAM) structure functioning as the drain, utilizing faceted epitaxy with pointed tips and a metal oxide layer for enhanced electric field enhancement and current conductivity, and a contact layer connecting the ReRAM structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional ReRAM structures are used with separate drains for each transistor, then each transistor can be independently controlled, but the device area increases and current density decreases
Solution Approach 1:
The patent combines the drain functions of multiple vertical FETs into a single shared drain structure formed by the ReRAM electrode. This merging approach allows multiple transistors to share common current path and control nodes, significantly reducing the overall device footprint while maintaining independent gate control for each transistor through separate channel regions.
Solution Approach 2:
The invention transitions from a planar two-dimensional layout to a three-dimensional vertical stacking architecture. Multiple FET channels are stacked vertically above the shared ReRAM drain, enabling higher current density by utilizing the vertical dimension for current flow while reducing the lateral device area required for integration.
2Reliability
If standard epitaxial structures are used, then fabrication is simpler, but electric field enhancement and current conductivity are insufficient
Solution Approach 1:
The patent introduces faceted epitaxial growth with pointed tips at specific locations within the ReRAM structure, particularly at the interface regions where electric field enhancement is most needed. This local modification of the crystal structure creates high field concentration zones that improve current conductivity and switching reliability without requiring complete restructuring of the entire device.
Solution Approach 2:
The invention employs composite material structures combining faceted epitaxial semiconductor layers with metal oxide resistance switching layers. The faceted epitaxial structure provides enhanced electric field concentration, while the metal oxide layer provides resistive switching functionality, creating a composite structure that achieves both high reliability and improved current characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for increased driven current and efficient integration of VTFETs with ReRAM, doubling the driven current for a given area and reducing electroforming randomness, while enabling high-density memory integration.
Implementation Method 1
utilizing faceted epitaxy with pointed tips and a metal oxide layer for enhanced electric field enhancement and current conductivity
Implementation Method 2
A typical ReRAM consists of a bottom electrode, a top electrode, and an oxide layer between the two electrodes
Data Source
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AI summary
A method may include forming two vertical transport field effect transistors stacked one atop the other and separated by a resistive random access memory structure. The two vertical transport field effect transistors may include a source (104, 112), a channel (106, 110), and a drain, wherein a contact layer (152) of the resistive random access memory strucure functions as the drain of the two vertical transport field effect transistors. Forming the two vertical transport field effect transistors may further include forming a first source (104) and a second source (112). The first source (104) is a bottom source and the second source (112) is a top source. The method may include forming a gate conductor layer (138, 140) surrounding the channel (106, 110). The resistive random access memory structures may include faceted epitaxy (144) defined by pointed tips. The pointed tips of the faceted epitaxy (144) may extend vertically toward each other. The faceted epitaxy (144) may be between the two vertical transport field effect transistors.