Vertically Stacked Resistive Switching Memory Device
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Solution Overview
Problem
Current non-volatile memory devices face challenges such as scaling limitations, high power consumption, and incompatibility with CMOS processes, particularly as transistor sizes approach sub-100 nm, leading to degraded performance and increased power dissipation.
Innovation Solution
A method and structure for forming a vertically stacked resistive switching device using a semiconductor substrate with multiple layers of memory cells, each comprising metal wiring structures and switching elements, allowing for high-density device formation compatible with existing CMOS processing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor-based memory devices are scaled down to sub-100 nm, then device density is improved, but performance degrades due to short channel effects and power dissipation increases
Solution Approach 1:
The patent transitions from planar 2D memory cell architecture to a 3D vertically stacked architecture. Multiple memory cell layers are stacked above each other, with each layer containing memory cells formed by intersecting word lines and bit lines. This vertical stacking enables higher device density without further scaling the lateral dimensions, thereby avoiding short channel effects while maintaining performance.
2Quantity of substance
If transistor-based memory devices are scaled down to sub-100 nm, then device density is improved, but power dissipation increases
Solution Approach 1:
By stacking memory cell layers vertically in the third dimension, the patent achieves higher device density without further reducing lateral feature sizes. This avoids the increased power dissipation associated with sub-100 nm scaling while still providing the desired density improvement.
3Reliability
If new materials and device structures are used for next generation memory devices, then performance characteristics are improved, but compatibility with CMOS processes is lost
Solution Approach 1:
The patent employs a resistive switching element that can be integrated with standard CMOS processing techniques. The memory cell structure uses conventional materials and fabrication processes compatible with CMOS, including the formation of switching elements between word lines and bit lines, enabling both high performance and ease of manufacture.
Data Source
AI summary
A memory device includes a first plurality of memory cells arranged in a first crossbar array, a first thickness of dielectric material overlying the first plurality of memory cells, and a second plurality of memory cells arranged in a second crossbar array overlying the first thickness of dielectric material. The memory device further includes a second thickness of dielectric material overlying the second plurality of memory cells. In a specific embodiment, the memory device further includes a Nth thickness of dielectric material overlying an Nth plurality of memory cells, where N is an integer ranging from 3 to 8.