Stacked Semiconductor BIST via Sequential Through-Electrode Control
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Solution Overview
Problem
Existing semiconductor technologies face challenges in performing built-in self-tests (BIST) on stacked semiconductor devices without causing instantaneous power drops and minimizing area increases due to additional circuitry requirements.
Innovation Solution
A stacked semiconductor device design that allows sequential or independent BIST on multiple chips through a network of through electrodes, with each chip having a test control circuit to manage test signals and commands, minimizing power drops and area increases by using existing signal lines for test operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BIST is performed on all stacked semiconductor chips simultaneously, then testing coverage is improved, but instantaneous power drop increases
Solution Approach 1:
The patent segments the simultaneous BIST operation into sequential phases, where chips are tested one at a time in a controlled sequence. The test control circuit activates test operations on individual chips sequentially rather than all chips simultaneously, dividing the power consumption demand into manageable time-staggered segments that prevent instantaneous power drops while maintaining complete testing coverage across all chips.
2Adaptability or versatility
If dedicated test circuits are added to each chip for independent BIST, then testing independence is improved, but device area increases
Solution Approach 1:
The patent implements multi-functional circuits that serve both normal operational functions and test functions. The signal transfer circuit and command reception circuit are designed to handle both regular data/command transmission and test signal transmission through the same physical pathways. This universal design allows each chip to perform independent BIST operations without requiring separate dedicated test circuitry, thereby achieving testing independence while minimizing area increase.
Solution Approach 2:
The patent merges the test control functionality into the existing operational control structures of each chip. The test control circuit integrates with the normal command and address generation circuits, allowing test commands to be generated and processed through the same infrastructure used for regular operations. This consolidation enables independent BIST capability while avoiding the area overhead of completely separate test circuitry.
3Measurement precision
If separate test signal lines are added for BIST operations, then test control precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the existing command and address signal lines multi-functional by enabling them to carry both normal operational signals and test control signals. The signal transfer circuit is configured to route test addresses and chip IDs through the same address and command lines used during normal operation, eliminating the need for separate test signal lines while maintaining precise test control through software-controlled signal multiplexing.
Data Source
AI summary
A stacked semiconductor device includes semiconductor chips, each including a signal transfer circuit respectively transferring a command, an address, and a chip select signal to first to third through electrodes, and respectively transferring a test address and a chip ID to the second and third through electrodes according to a test control signal; a command reception circuit transferring a test command or a signal transferred from the first through electrode to an internal circuit when a signal transferred from the third through electrode is identical to the chip ID coincide with each other; and a test control circuit activating the test control signal according to deactivation of a test control signal of an upper chip, and generating the test command and the test address according to the test control signal.