Stacked Semiconductor Chip Rear Surface Bonding
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Solution Overview
Problem
Current semiconductor package technologies face challenges in achieving high integration density and efficient electrical connectivity between semiconductor chips, particularly in compact chip scale package (CSP) techniques.
Innovation Solution
The method involves bonding rear surfaces of semiconductor chips to each other, forming encapsulation portions, via plugs, insulating layers, and package pads to establish electrical connections, and creating redistribution structures for enhanced connectivity and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked to increase integration density, then the number of chips per package is increased, but the complexity of electrical connection between chips increases
Solution Approach 1:
The patent divides the electrical connection system into modular components: bonding pads on individual chips, via plugs through encapsulation layers, and routing interconnections. This segmentation allows each component to be optimized independently while simplifying the overall connection architecture between stacked chips.
Solution Approach 2:
The patent transitions from planar electrical connections to three-dimensional vertical connections by stacking chips and using via plugs to pass through encapsulation portions. This dimensional change enables efficient electrical connectivity in the vertical direction, reducing the complexity of routing connections between multiple stacked chips.
2Area of moving object
If chip size is reduced to achieve compact CSP packaging, then package size is decreased, but the area available for electrical connections is reduced
Solution Approach 1:
The patent moves electrical connections from the horizontal plane to the vertical dimension by implementing via plugs that pass through encapsulation portions between stacked chips. This allows connection areas to be distributed across multiple vertical layers, effectively increasing total connection area without increasing the horizontal package footprint.
Solution Approach 2:
The bonding pads serve multiple functions: they provide electrical connections for the active circuitry on the chip front surface and simultaneously serve as connection points for the bonding process between stacked chips. This multi-functionality maximizes the utilization of limited chip area for both connectivity and packaging purposes.
3Reliability
If multiple encapsulation portions are formed to encapsulate stacked chips, then structural protection is improved, but the number of manufacturing steps increases
Solution Approach 1:
The patent combines multiple encapsulation portions into a unified encapsulation structure that simultaneously protects multiple stacked chips. The via plugs are formed to pass through these encapsulation portions, integrating the protective function with the electrical connection function in a single manufacturing flow, thereby reducing the number of discrete steps required.
Data Source
AI summary
A semiconductor package and module, and methods of fabricating the same are provided. A method of fabricating a semiconductor package may include bonding rear surfaces of first and second semiconductor chips to each other, each of the semiconductor chips having chip pads exposed on front surfaces. The method may also include forming an encapsulation portion configured to encapsulate side surfaces of the bonded semiconductor chips, forming via plugs configured to pass through the encapsulation portion, forming an insulating layer configured to expose surfaces of the chip pads and the via plugs on the exposed surfaces of the two semiconductor chips and surfaces of the encapsulation portion, and forming package pads on the exposed surfaces of the chip pads and the surfaces of the via plugs.