Stacked Semiconductor Package Direct Copper Through Electrode Connection
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Solution Overview
Problem
Conventional stacked semiconductor packages face high manufacturing costs due to expensive bump and solder ball formation, poor electrical reliability, and chip strength issues resulting from thin back grinding, which complicates ion gettering and handling.
Innovation Solution
A stacked semiconductor package design featuring direct electrical connections between upper and lower chips through polymer layers and through electrodes, eliminating the need for bumps and solder balls, and reducing the complexity of support substrate processes, while maintaining ion gettering properties through controlled back grinding post-stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bumps and solder balls are used for connecting upper and lower semiconductor chips, then electrical connections can be established, but manufacturing costs increase and electrical reliability decreases due to higher resistance compared to copper
Solution Approach 1:
The invention extracts and eliminates the bump and solder ball components from the electrical connection structure. Instead of using these intermediate connection elements, the patent directly exposes and connects the copper through electrodes from the lower chip to the upper chip, removing the high-resistance solder ball layer and reducing manufacturing complexity
Solution Approach 2:
The invention changes the material parameter of the electrical connection from solder ball (high resistance) to copper (low resistance). By maintaining the copper material throughout the through electrode and connection structure, the patent achieves lower resistance and better electrical reliability while simplifying the manufacturing process
2Reliability
If the wafer is back ground thinly to improve ion gettering properties, then ion gettering is enhanced, but chip strength decreases and chips may be damaged during handling
Solution Approach 1:
The invention performs the back grinding process after the chips are stacked together rather than before stacking. This preliminary action of stacking first allows the chips to gain structural support from each other, and then the thin back grinding can be performed safely without compromising individual chip strength, as the stacked structure provides mechanical support
Solution Approach 2:
The invention merges multiple chips into a stacked structure before performing back grinding. By combining the chips vertically with direct copper electrode connections, the stacked assembly gains collective strength that enables safe thin grinding for ion gettering without damaging individual chips
3Manufacturing precision
If support substrate attaching and detaching processes are performed on respective wafers to accomplish thinning, then chip thinning is achieved, but manufacturing costs increase due to expensive processes
Solution Approach 1:
The invention merges multiple wafer processing operations into a single integrated process. By stacking the chips with protruding through electrodes directly, the need for separate support substrate attaching and detaching processes for each wafer is eliminated, reducing manufacturing steps and costs while achieving the same thinning result
Solution Approach 2:
The invention extracts and removes the support substrate from the manufacturing process entirely. Instead of using support substrates for each wafer during thinning, the patent uses the stacked chip structure itself with direct copper electrode exposure to achieve the required thickness and electrical connection, eliminating expensive support substrate materials and processes
Data Source
AI summary
A stacked semiconductor package includes: a first semiconductor chip formed with a first through electrode, the first through electrode protruding above a first surface of the first semiconductor chip; a first polymer layer formed over the first surface of the first semiconductor chip such that the first through electrode is exposed by the first polymer layer; a second semiconductor chip having a first surface attached onto the first semiconductor chip by medium of the first polymer layer and a vial hole passing through the second semiconductor chip, the first surface of the second semiconductor chip being formed with a bonding pad having a through hole which corresponds to the first through electrode; and a second through electrode located within the through hole and the via hole and is electrically connected with the first through electrode.