Stacked Semiconductor Device Data Bus Inversion Circuit
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Solution Overview
Problem
Current semiconductor technologies face challenges in efficiently transmitting data between stacked semiconductor chips, particularly in reducing current consumption and noise during data input/output operations in three-dimensional stacked semiconductor devices.
Innovation Solution
The implementation of a stacked semiconductor device with a base die and multiple core dies connected through through-electrodes, which includes an input buffer, parallel circuit, and write inversion circuit to sort and invert data bits, supporting data bus inversion (DBI) functions for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data is transmitted directly between stacked semiconductor chips without sorting and inversion, then the device complexity is reduced, but current consumption increases and noise is generated due to excessive data transitions
Solution Approach 1:
The patent applies preliminary action by performing data sorting and inversion operations in advance before data transmission. The input buffer sorts consecutive bits of write data to be positioned adjacent to each other, and the write inversion circuit inverts data based on transition counts. This preliminary processing minimizes data transitions during transmission, reducing current consumption without adding complex real-time control mechanisms during data transfer.
2Loss of energy
If data sorting and inversion circuits are added to reduce current consumption, then energy efficiency improves, but the device complexity increases
Solution Approach 1:
The patent segments the data processing function across multiple components: the input buffer handles data sorting, while the write inversion circuit in each core die handles data inversion. This segmentation allows each component to perform a specific function efficiently, reducing overall energy loss while distributing the complexity across manageable modules rather than concentrating it in a single complex unit.
Solution Approach 2:
Each core die includes its own write inversion circuit that autonomously determines whether to invert data based on the number of transitions in received write data. This self-service approach allows each die to independently optimize its energy consumption without requiring centralized control, reducing energy loss while keeping the overall system architecture relatively simple.
3Object-generated harmful factors
If data transitions are minimized through sorting and inversion, then noise is reduced, but additional circuits are required increasing device complexity
Solution Approach 1:
The input buffer performs preliminary sorting of write data to position consecutive bits adjacent to each other before transmission. This preliminary action reduces the number of transitions that would otherwise occur during data transmission, thereby reducing noise. By performing this sorting in advance in a dedicated buffer, the patent avoids the need for complex real-time switching circuits that would increase device complexity.
Solution Approach 2:
The input buffer acts as an intermediary between the data source and the transmission medium. It sorts and prepares the data before transmission, reducing noise-generating transitions. This intermediary approach allows noise reduction without requiring complex noise filtering circuits in the transmission path, as the problem is addressed at the data preparation stage instead.
Data Source
AI summary
A stacked semiconductor device includes a base die including an input buffer and a parallel circuit; and a plurality of core dies stacked over the base die, the core dies coupled to the base die through a plurality of through-electrodes, wherein the input buffer receives write data in a first order and a write inversion signal, the parallel circuit sorts consecutive bits of the write data to be positioned adjacent to each other so that the write data becomes first parallel data and to transfer the first parallel data to respective first to n-th internal input/output lines, and each of the core dies includes an input control circuit to re-sort the first parallel data transferred via the respective first to n-th internal I/O lines into the write data and a write inversion circuit to selectively invert the re-sorted write data according to the write inversion signal.