Stacked Semiconductor Package with Dual Mold Sealing
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Solution Overview
Problem
Current semiconductor packages face challenges in reducing the outer size while effectively sealing and protecting multiple semiconductor chips, such as NAND flash memories and controllers, from external stress, humidity, and contaminants, especially when trying to stack NAND chips above a controller chip with different pad arrangements.
Innovation Solution
A semiconductor package design that includes a substrate with a controller chip and NAND chips sealed by mold members, where the controller chip is sealed by a first mold member and the NAND chips are sealed by a second mold member, allowing for a reduced outer size by stacking NAND chips above the controller chip with specific wire and mount film arrangements, and using multi-layered wiring substrates and different resin materials for the mold members.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are sealed in one package using a mold type structure, then the integration is improved, but the outer size becomes large
Solution Approach 1:
The patent transitions from a planar arrangement of semiconductor chips to a three-dimensional stacked configuration. Multiple NAND flash memory chips are vertically stacked above the controller chip, utilizing the vertical dimension to increase integration density while reducing the horizontal footprint of the package.
Solution Approach 2:
The patent implements a nested structure where smaller semiconductor chips (NAND flash memory chips) are stacked and integrated above a larger controller chip. This nesting arrangement allows multiple functional components to be compactly organized within a single package, improving integration while minimizing overall package size.
2Area of stationary object
If NAND chips are stacked above controller chip, then the outer size is reduced, but the sealing and protection from external stress becomes difficult
Solution Approach 1:
The patent divides the sealing function into multiple segments: a first mold member seals the controller chip, while a second mold member seals the stacked NAND flash memory chips. This segmentation allows each mold member to be optimized for its specific sealing requirements, providing effective protection against external stress while maintaining the reduced outer size achieved through vertical stacking.
Solution Approach 2:
The patent employs different resin materials for the first and second mold members to optimize protection against external stress. By selecting appropriate composite materials with suitable mechanical properties, the package achieves both compact dimensions and enhanced reliability for protecting the stacked semiconductor chips from external environmental factors.
3Reliability
If different resin materials are used for mold members, then the protection effectiveness is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the molding process into two separate steps, each using a different resin material optimized for specific protection requirements. The first mold member is formed with a first resin material to seal the controller chip, and the second mold member is formed with a second resin material to seal the NAND flash memory chips. This segmentation enables tailored protection effectiveness while maintaining manufacturing feasibility through sequential processing.
Data Source
AI summary
According to one embodiment, a semiconductor package includes a substrate with first and second pad, first semiconductor chip above the substrate, first wire, first mold member, second semiconductor chip above the first mold member, third semiconductor chip above the second semiconductor chip, second wire, and a second mold member. The first wire electrically connects the first pad and the first semiconductor chip. The first mold member seals the first wire and the first semiconductor chip. The second wire electrically connects the second pad and the second semiconductor chip. The second mold member seals the second wire, the second and the third semiconductor chips, and the first mold member.