3D Stacked Semiconductor Channels With Dummy Gate Layer
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved reliability and integration density in three-dimensional semiconductor devices.
Innovation Solution
A three-dimensional semiconductor device design featuring vertically stacked transistors with a gate electrode that encloses channel patterns, including a first and second active region with different thicknesses and work function metals, and a dummy channel pattern to enhance reliability and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for small pattern size, then pattern size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar MOS-FETs to three-dimensional vertically stacked transistors. Multiple channel patterns (first, second, third channel patterns) are stacked vertically to form a three-dimensional structure, allowing increased integration density while maintaining adequate channel dimensions for reliable operation. The gate electrode wraps around these vertical channels, providing gate control in a three-dimensional configuration that preserves operational properties despite reduced footprint area.
Solution Approach 2:
The gate electrode is configured to wrap around and enclose the channel patterns, with the gate insulating layer nested between the gate electrode and channel patterns. The source and drain patterns are positioned to surround the channel patterns vertically. This nested configuration allows multiple functional layers to be integrated in a compact vertical space, achieving high integration density while maintaining proper electrical isolation and control for reliable device operation.
2Productivity
If more transistors are integrated to increase integration density, then integration density increases, but device area increases
Solution Approach 1:
The patent employs vertical stacking of multiple channel patterns (first, second, third channel patterns) and corresponding source/drain patterns to create a three-dimensional transistor structure. This vertical arrangement allows multiple transistors to be integrated within a small footprint area on the substrate, dramatically increasing integration density without proportionally increasing the lateral device area.
Solution Approach 2:
Multiple channel patterns and source/drain patterns are merged into a single vertical stack structure that is controlled by a common gate electrode. The gate insulating layer uniformly separates the gate electrode from all channel patterns in the stack. This merged configuration allows multiple transistor functions to be combined in a compact vertical arrangement, achieving high integration density while minimizing the lateral area occupied by the device.
3Manufacturing precision
If different metal patterns with varying work functions are used, then threshold voltage control improves, but device complexity increases
Solution Approach 1:
The patent applies different work function metals to specific regions of the gate electrode structure. A first work function metal is used in a first region of the gate electrode, while a second work function metal is used in a second region. This local differentiation allows precise control of threshold voltages for different channel patterns within the same device, enabling independent optimization of electrical characteristics for each transistor in the stack while maintaining a unified gate structure.
Data Source
AI summary
Three-dimensional (3D) semiconductor device may include a first active region on a substrate, the first active region including a lower channel pattern and a pair of lower source/drain patterns that are on opposing side surfaces of the lower channel pattern respectively, a second active region stacked on the first active region, the second active region including an upper channel pattern and a pair of upper source/drain patterns that are on opposing side surfaces of the upper channel pattern, respectively, a dummy channel pattern between the lower and upper channel patterns, a pair of liner layers that are on opposing side surfaces of the dummy channel pattern, respectively, and a gate electrode on the lower, dummy, and upper channel patterns. The gate electrode may include a lower gate electrode on the lower channel pattern and an upper gate electrode on the upper channel pattern.