Stacked Semiconductor ESD Protection via Through Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-chip semiconductor devices require significant surface area for ESD protection circuitry on each semiconductor device, which can be inefficient and limit the number of chips that can be produced on a single silicon wafer.
Innovation Solution
Implementing through vias to connect ESD protection circuitry on a bottom chip in a stacked semiconductor package to external connections, allowing only the bottom chip to have ESD protection circuitry, thereby reducing the need for it on other chips and optimizing area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection circuitry is implemented on each semiconductor device in a multi-chip package, then ESD protection reliability is improved, but surface area consumption increases
Solution Approach 1:
The patent divides the ESD protection function across multiple chips in a stacked configuration, with each chip having its own ESD protection circuitry. This segmentation allows the system to achieve comprehensive ESD protection reliability while distributing the surface area requirement across multiple smaller chips rather than requiring one large chip with all protection circuitry.
Solution Approach 2:
The patent transitions from a two-dimensional layout where all ESD protection circuitry would be on a single chip to a three-dimensional stacked configuration. By stacking multiple chips vertically and connecting them through through-silicon vias (TSVs), the system achieves the required ESD protection functionality while significantly reducing the footprint surface area on each individual chip.
2Reliability
If ESD protection circuitry is implemented on each semiconductor device, then protection coverage is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements a universal ESD protection architecture where multiple chips share a common ESD protection structure through TSV connections. This multi-functional design allows the same ESD protection circuitry to protect multiple chips simultaneously, reducing redundant manufacturing steps and lowering overall production costs compared to implementing independent protection circuits on each chip.
Solution Approach 2:
The patent merges the ESD protection functionality across multiple chips by connecting them through TSVs to a shared protection structure. This consolidation reduces the total number of ESD protection circuits needed, simplifies the manufacturing process, and decreases material requirements, thereby reducing manufacturing costs while maintaining comprehensive protection coverage.
3Reliability
If ESD protection circuitry is placed on all chips in a stack, then ESD protection effectiveness is improved, but area efficiency deteriorates
Solution Approach 1:
The patent applies local quality by implementing ESD protection circuitry only on specific chips within the stack that are most vulnerable to ESD events, such as the bottom chip that directly interfaces with external connections. Less critical chips in the stack have reduced or no ESD protection circuitry, optimizing the distribution of protection resources and improving area efficiency while maintaining effective protection where it is most needed.
Data Source
AI summary
A multi-chip stack can include a first semiconductor device disposed between a plurality of electrical connections and the second semiconductor device. The first semiconductor device can include a first through via and a first electrostatic discharge (ESD) protection circuit connected to a first one of the electrical connections. The first ESD Protection circuit can have a first ESD protection structure. The first through via provides an electrical connection through the first semiconductor device from a first surface to an opposite surface of the first semiconductor device and between the first one of the plurality of electrical connections and a first terminal of the first circuit. The first terminal of the first circuit can be free of an electrical connection to an ESD protection circuit having the first ESD protection structure formed on the second semiconductor device.